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{
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  "tree": "3e95bfbaac8fe0603b9f34e738f945da3b471893",
  "parents": [
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  "author": {
    "name": "Dave Williams",
    "email": "dave.williams@ensilica.com",
    "time": "Mon Jan 31 19:08:28 2022 +0000"
  },
  "committer": {
    "name": "weicaiyang",
    "email": "49293026+weicaiyang@users.noreply.github.com",
    "time": "Wed Apr 06 14:09:45 2022 -0700"
  },
  "message": "[sw,tests] SRAM scrambled access tests DV integration\n\nChecks that known data written to main and retention SRAMs is unreadable once the memories have been scrambled.\n\nSigned-off-by: Dave Williams \u003cdave.williams@ensilica.com\u003e\n",
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