hw/top_earlgrey/syn/top_earlgrey_batch_syn_cfg.hjson

// Copyright lowRISC contributors.
// Licensed under the Apache License, Version 2.0, see LICENSE for details.
// SPDX-License-Identifier: Apache-2.0
{
  // This is a cfg hjson group for synthesis.
  // It includes all synthesis setups used in top_earlgrey.
  name: top_earlgrey_batch_syn

  import_cfgs: [// Project wide common cfg file
                "{proj_root}/hw/data/common_project_cfg.hjson"]

  flow: syn

  // Maintain alphabetical order below.
  use_cfgs: [// Block-level synthesis flows.
             "{proj_root}/hw/ip/aes/syn/aes_syn_cfg.hjson",
             "{proj_root}/hw/ip/keymgr/syn/keymgr_syn_cfg.hjson",
             "{proj_root}/hw/ip/kmac/syn/kmac_syn_cfg.hjson",
             "{proj_root}/hw/ip/lc_ctrl/syn/lc_ctrl_syn_cfg.hjson",
             "{proj_root}/hw/ip/otbn/syn/otbn_syn_cfg.hjson",
             "{proj_root}/hw/ip/otp_ctrl/syn/otp_ctrl_syn_cfg.hjson",
             "{proj_root}/hw/ip/rv_core_ibex/syn/rv_core_ibex_syn_cfg.hjson",
             // Top-level synthesis flows.
             // TODO: align Verilator and ASIC versions.
             "{proj_root}/hw/top_earlgrey/syn/chip_earlgrey_asic_syn_cfg.hjson"]
}