hw/ip/lc_ctrl/dv/lc_ctrl_sim_cfg.hjson

// Copyright lowRISC contributors.
// Licensed under the Apache License, Version 2.0, see LICENSE for details.
// SPDX-License-Identifier: Apache-2.0
{
  // Name of the sim cfg - typically same as the name of the DUT.
  name: lc_ctrl

  // Top level dut name (sv module).
  dut: lc_ctrl

  // Top level testbench name (sv module).
  tb: tb

  // Simulator used to sign off this block
  tool: vcs

  // Fusesoc core file used for building the file list.
  fusesoc_core: lowrisc:dv:lc_ctrl_sim:0.1

  // Testplan hjson file.
  testplan: "{proj_root}/hw/ip/lc_ctrl/data/lc_ctrl_testplan.hjson"

  // RAL spec - used to generate the RAL model.
  ral_spec: "{proj_root}/hw/ip/lc_ctrl/data/lc_ctrl.hjson"

  // Import additional common sim cfg files.
  // TODO: remove imported cfgs that do not apply.
  import_cfgs: [// Project wide common sim cfg file
                "{proj_root}/hw/dv/tools/dvsim/common_sim_cfg.hjson",
                // Common CIP test lists
                "{proj_root}/hw/dv/tools/dvsim/tests/csr_tests.hjson",
                "{proj_root}/hw/dv/tools/dvsim/tests/alert_test.hjson",
                "{proj_root}/hw/dv/tools/dvsim/tests/tl_access_tests.hjson",
                "{proj_root}/hw/dv/tools/dvsim/tests/sec_cm_tests.hjson",
                "{proj_root}/hw/dv/tools/dvsim/tests/stress_tests.hjson"]

  // Add additional tops for simulation.
  sim_tops: ["lc_ctrl_bind", "lc_ctrl_cov_bind",
             "sec_cm_prim_sparse_fsm_flop_bind", "sec_cm_prim_onehot_check_bind"]

  // Default iterations for all tests - each test entry can override this.
  reseed: 50

  overrides: [
    //
    // Override coverage config files to add our elaboration time coverage exclusions etc.
    //
    {
      name: default_vcs_cov_cfg_file
      value: "-cm_hier {dv_root}/tools/vcs/cover.cfg+{dv_root}/tools/vcs/common_cov_excl.cfg+{proj_root}/hw/ip/lc_ctrl/dv/cov/lc_ctrl_cover.cfg"
    }
    // The jtag agent requires the data and bytenable widths to be increased.
    {
      name: tl_dw
      value: 64
    }
    {
      name: tl_dbw
      value: 8
    }
  ]

  // Add LC_CTRL specific exclusion files.
  vcs_cov_excl_files: ["{proj_root}/hw/ip/lc_ctrl/dv/cov/lc_ctrl_cov_unr_excl.el",
                       "{proj_root}/hw/ip/lc_ctrl/dv/cov/lc_ctrl_terminal_st_excl.el"]

  // Default UVM test and seq class name.
  uvm_test: lc_ctrl_base_test
  uvm_test_seq: lc_ctrl_base_vseq

  // List of test specifications.
  tests: [
    {
      name: lc_ctrl_smoke
      uvm_test_seq: lc_ctrl_smoke_vseq
    }

    {
      name: lc_ctrl_state_failure
      uvm_test_seq: lc_ctrl_state_failure_vseq
    }

    {
      name: lc_ctrl_state_post_trans
      uvm_test_seq: lc_ctrl_state_post_trans_vseq
    }

    {
      name: lc_ctrl_prog_failure
      uvm_test_seq: lc_ctrl_prog_failure_vseq
    }

    {
      name: lc_ctrl_errors
      uvm_test_seq: lc_ctrl_lc_errors_vseq
    }

    {
      name: lc_ctrl_security_escalation
      uvm_test_seq: lc_ctrl_security_escalation_vseq
    }

    {
      name: lc_ctrl_regwen_during_op
      uvm_test_seq: lc_ctrl_regwen_during_op_vseq
      reseed: 10
    }

    {
      name: lc_ctrl_jtag_smoke
      uvm_test_seq: lc_ctrl_smoke_vseq
      run_opts: ["+jtag_csr=1", "+create_jtag_riscv_map=1"]
      reseed: 20
    }

    {
      name: lc_ctrl_jtag_state_failure
      uvm_test_seq: lc_ctrl_state_failure_vseq
      run_opts: ["+jtag_csr=1", "+create_jtag_riscv_map=1"]
      reseed: 20
    }

    {
      name: lc_ctrl_jtag_state_post_trans
      uvm_test_seq: lc_ctrl_state_post_trans_vseq
      run_opts: ["+jtag_csr=1", "+create_jtag_riscv_map=1"]
      reseed: 20
    }

    {
      name: lc_ctrl_jtag_prog_failure
      uvm_test_seq: lc_ctrl_prog_failure_vseq
      run_opts: ["+jtag_csr=1", "+create_jtag_riscv_map=1"]
      reseed: 20
    }

    {
      name: lc_ctrl_jtag_errors
      uvm_test_seq: lc_ctrl_lc_errors_vseq
      run_opts: ["+jtag_csr=1", "+create_jtag_riscv_map=1"]
      reseed: 20
    }

    {
      name: lc_ctrl_jtag_access
      uvm_test_seq: lc_ctrl_jtag_access_vseq
      run_opts: ["+en_scb=0", "+create_jtag_riscv_map=1"]
      reseed: 50
    }

    {
      name: lc_ctrl_jtag_priority
      uvm_test_seq: lc_ctrl_jtag_priority_vseq
      run_opts: ["+en_scb=0", "+create_jtag_riscv_map=1"]
      reseed: 10
    }

    {
      name: lc_ctrl_jtag_regwen_during_op
      uvm_test_seq: lc_ctrl_regwen_during_op_vseq
      run_opts: ["+jtag_csr=1", "+create_jtag_riscv_map=1"]
      reseed: 10
    }

    {
      name: "lc_ctrl_jtag_csr_hw_reset"
      build_mode: "cover_reg_top"
      uvm_test_seq: "lc_ctrl_common_vseq"
      run_opts: ["+csr_hw_reset", "+jtag_csr=1", "+create_jtag_riscv_map=1"]
      en_run_modes: ["csr_tests_mode"]
      reseed: 10
    }

    {
      name: "lc_ctrl_jtag_csr_rw"
      build_mode: "cover_reg_top"
      uvm_test_seq: "lc_ctrl_common_vseq"
      run_opts: ["+csr_rw", "+jtag_csr=1", "+create_jtag_riscv_map=1"]
      en_run_modes: ["csr_tests_mode"]
      reseed: 10
    }

    {
      name: "lc_ctrl_jtag_csr_bit_bash"
      build_mode: "cover_reg_top"
      uvm_test_seq: "lc_ctrl_common_vseq"
      run_opts: ["+csr_bit_bash", "+jtag_csr=1", "+create_jtag_riscv_map=1"]
      en_run_modes: ["csr_tests_mode"]
      reseed: 10
    }

    {
      name: "lc_ctrl_jtag_csr_aliasing"
      build_mode: "cover_reg_top"
      uvm_test_seq: "lc_ctrl_common_vseq"
      run_opts: ["+csr_aliasing", "+jtag_csr=1", "+create_jtag_riscv_map=1"]
      en_run_modes: ["csr_tests_mode"]
      reseed: 10
    }

    {
      name: "lc_ctrl_jtag_same_csr_outstanding"
      build_mode: "cover_reg_top"
      uvm_test_seq: "lc_ctrl_common_vseq"
      run_opts: ["+run_same_csr_outstanding", "+jtag_csr=1", "+create_jtag_riscv_map=1"]
      en_run_modes: ["csr_tests_mode"]
      reseed: 10
    }

    {
      name: "lc_ctrl_jtag_csr_mem_rw_with_rand_reset"
      build_mode: "cover_reg_top"
      uvm_test_seq: "lc_ctrl_common_vseq"
      run_opts: ["+run_csr_mem_rw_with_rand_reset", "+test_timeout_ns=10000000000",  "+jtag_csr=1",
                 "+create_jtag_riscv_map=1"]
      en_run_modes: ["csr_tests_mode"]
      reseed: 10
    }

    {
      name: "lc_ctrl_jtag_alert_test"
      build_mode: "cover_reg_top"
      uvm_test_seq: "lc_ctrl_common_vseq"
      run_opts: ["+run_alert_test", "+en_scb=0", "+jtag_csr=1", "+create_jtag_riscv_map=1"]
      reseed: 10
    }

    {
      name: "lc_ctrl_sec_mubi"
      uvm_test_seq: lc_ctrl_sec_mubi_vseq
      run_opts: ["+create_jtag_riscv_map=1"]
    }

    {
      name: "lc_ctrl_sec_token_mux"
      uvm_test_seq: lc_ctrl_sec_token_mux_vseq
      run_opts: ["+create_jtag_riscv_map=1"]
    }

    {
      name: "lc_ctrl_sec_token_digest"
      uvm_test_seq: lc_ctrl_sec_token_digest_vseq
      run_opts: ["+create_jtag_riscv_map=1"]
    }

    {
      name: "lc_ctrl_stress_all"
      uvm_test_seq: lc_ctrl_stress_all_vseq
      run_opts: ["+create_jtag_riscv_map=1"]
    }

    {
      name: "lc_ctrl_stress_all_with_rand_reset"
      run_opts: ["+create_jtag_riscv_map=1"]
    }
  ]

  // List of regressions.
  regressions: [
    {
      name: smoke
      tests: ["lc_ctrl_smoke",
              "lc_ctrl_jtag_smoke"]
    }
    {
      name: jtag
      tests : [ "lc_ctrl_jtag_access",
              "lc_ctrl_jtag_priority",
              "lc_ctrl_jtag_smoke",
              "lc_ctrl_jtag_state_post_trans",
              "lc_ctrl_jtag_errors",
              "lc_ctrl_jtag_prog_failure",
              "lc_ctrl_jtag_regwen_during_op",
              "lc_ctrl_jtag_csr_hw_reset",
              "lc_ctrl_jtag_csr_rw",
              "lc_ctrl_jtag_csr_bit_bash",
              "lc_ctrl_jtag_csr_aliasing",
              "lc_ctrl_jtag_same_csr_outstanding",
              "lc_ctrl_jtag_csr_mem_rw_with_rand_reset",
              "lc_ctrl_jtag_alert_test"
      ]
    }
  ]
}