tree 033a3af8f196a9255ad8034f4c47ad32f48c5fe7
parent ed57feb6194802619cbdf323a14dfef65fc711f6
author Pirmin Vogel <vogelpi@lowrisc.org> 1601644238 +0200
committer Pirmin Vogel <vogelpi@lowrisc.org> 1601888184 +0200

[fpga] Constrain JTAG and SPI clocks

This commit makes sure the JTAG and SPI clock signals are constrained
(currently to 10 MHz just like the main system clock on FPGA).
Previously, they were both unconstrained which might have caused issues.

This is related to lowRISC/OpenTitan#3606.

Signed-off-by: Pirmin Vogel <vogelpi@lowrisc.org>