tree c08a291b39ee91f8a4a875b7c50628f494938fa5
parent bdfe75e1b440cee78d334c2b343eb9135e3dfd2a
author Timothy Chen <timothytim@google.com> 1631659666 -0700
committer tjaychen <timothytim@google.com> 1631834506 -0700

[top] Integrating ast into verilator

- This is a preparatory step for #7349 and eventual common chip level template
- SYNTHESIS is replaced with AST_BYPASS_CLK inside the oscillator modules
  because verilator sims are not actually "synthesis". There are other parameters in the system that depend on the SYNTHESIS flag not being set.

Signed-off-by: Timothy Chen <timothytim@google.com>