User Guides

• Getting Started
  • Getting started
  • Quickstart
  • Notes on using GitHub and local git
  • Build software
  • Getting started with Verilator
  • Getting started on FPGAs
    • Obtaining an FPGA board
    • Installing Xilinx Vivado
  • Getting started with a design <Coming Soon>
  • Getting started with verification <Coming Soon>
• Work with hardware code in external repositories
• Design Methodology
  • Importance of Verilog Style Guide
  • Explanation of Comportability concept
  • Milestones and Tracking
  • Documentation
  • Register Tool Usage
  • Linting Methodology
  • Assertions Methodology
  • CDC Methodology
  • DFT
  • Generated Code
• Verification Methodology <Coming Soon>
  • Verification strategy overview
  • How do we define Verification completion
    • Current verification status of IP and definition of milestones
  • Tools
  • Test planning
  • Progress and tracking
  • Code coverage output
    • How do we report status
  • Overview of in-tree helper classes, test benches, etc.
• Validation Methodology <Coming Soon>
  • How to download bit stream
  • What tests exist today
  • How to run tests
  • How does this differ from verification
  • How to add tests
• List of Top-Level Designs