diff --git a/hw/ip/spi_device/data/spi_device.hjson b/hw/ip/spi_device/data/spi_device.hjson
index c3c47a6..f175a59 100644
--- a/hw/ip/spi_device/data/spi_device.hjson
+++ b/hw/ip/spi_device/data/spi_device.hjson
@@ -25,28 +25,28 @@
     }
   ]
   interrupt_list: [
-    { name: "rx_full"
+    { name: "generic_rx_full"
       desc: "RX SRAM FIFO Full"
     }
-    { name: "rx_watermark"
+    { name: "generic_rx_watermark"
       desc: "RX SRAM FIFO is above the level"
     }
-    { name: "tx_watermark"
+    { name: "generic_tx_watermark"
       desc: "TX SRAM FIFO is under the level"
     }
-    { name: "rx_error"
+    { name: "generic_rx_error"
       desc: "SDI in FwMode has error"
     }
-    { name: "rx_overflow"
+    { name: "generic_rx_overflow"
       desc: "RX Async FIFO overflow"
     }
-    { name: "tx_underflow"
+    { name: "generic_tx_underflow"
       desc: "TX Async FIFO underflow"
     }
-    { name: "cmdfifo_not_empty"
+    { name: "upload_cmdfifo_not_empty"
       desc: "Upload Command FIFO is not empty"
     }
-    { name: "payload_not_empty"
+    { name: "upload_payload_not_empty"
       desc: '''Upload paylod is not empty.
 
         The event occurs after SPI transaction completed
diff --git a/hw/ip/spi_device/dv/tb/tb.sv b/hw/ip/spi_device/dv/tb/tb.sv
index 2760e81..027b009 100644
--- a/hw/ip/spi_device/dv/tb/tb.sv
+++ b/hw/ip/spi_device/dv/tb/tb.sv
@@ -64,14 +64,14 @@
 
     .cio_tpm_csb_i  (1'b 1     ), // TODO: Add TPM agent
 
-    .intr_rx_full_o             (intr_rxf  ),
-    .intr_rx_watermark_o        (intr_rxlvl),
-    .intr_tx_watermark_o        (intr_txlvl),
-    .intr_rx_error_o            (intr_rxerr),
-    .intr_rx_overflow_o         (intr_rxoverflow),
-    .intr_tx_underflow_o        (intr_txunderflow),
-    .intr_cmdfifo_not_empty_o   (intr_cmdfifo_not_empty),
-    .intr_payload_not_empty_o   (intr_payload_not_empty),
+    .intr_generic_rx_full_o             (intr_rxf  ),
+    .intr_generic_rx_watermark_o        (intr_rxlvl),
+    .intr_generic_tx_watermark_o        (intr_txlvl),
+    .intr_generic_rx_error_o            (intr_rxerr),
+    .intr_generic_rx_overflow_o         (intr_rxoverflow),
+    .intr_generic_tx_underflow_o        (intr_txunderflow),
+    .intr_upload_cmdfifo_not_empty_o   (intr_cmdfifo_not_empty),
+    .intr_upload_payload_not_empty_o   (intr_payload_not_empty),
     .intr_readbuf_watermark_o   (intr_readbuf_watermark),
     .intr_readbuf_flip_o        (intr_readbuf_flip),
     .intr_tpm_header_not_empty_o(intr_tpm_header_not_empty),
diff --git a/hw/ip/spi_device/rtl/spi_device.sv b/hw/ip/spi_device/rtl/spi_device.sv
index eccc869..6a38e6f 100644
--- a/hw/ip/spi_device/rtl/spi_device.sv
+++ b/hw/ip/spi_device/rtl/spi_device.sv
@@ -38,16 +38,16 @@
 
   // Interrupts
   // INTR: Generic mode
-  output logic intr_rx_full_o,              // RX FIFO Full
-  output logic intr_rx_watermark_o,         // RX FIFO above level
-  output logic intr_tx_watermark_o,         // TX FIFO below level
-  output logic intr_rx_error_o,             // RX Frame error
-  output logic intr_rx_overflow_o,          // RX Async FIFO Overflow
-  output logic intr_tx_underflow_o,         // TX Async FIFO Underflow
+  output logic intr_generic_rx_full_o,              // RX FIFO Full
+  output logic intr_generic_rx_watermark_o,         // RX FIFO above level
+  output logic intr_generic_tx_watermark_o,         // TX FIFO below level
+  output logic intr_generic_rx_error_o,             // RX Frame error
+  output logic intr_generic_rx_overflow_o,          // RX Async FIFO Overflow
+  output logic intr_generic_tx_underflow_o,         // TX Async FIFO Underflow
 
   // INTR: Flash mode
-  output logic intr_cmdfifo_not_empty_o,
-  output logic intr_payload_not_empty_o,
+  output logic intr_upload_cmdfifo_not_empty_o,
+  output logic intr_upload_payload_not_empty_o,
   output logic intr_readbuf_watermark_o,
   output logic intr_readbuf_flip_o,
 
@@ -472,79 +472,79 @@
   prim_intr_hw #(.Width(1)) u_intr_rxf (
     .clk_i,
     .rst_ni,
-    .event_intr_i           (intr_sram_rxf_full          ),
-    .reg2hw_intr_enable_q_i (reg2hw.intr_enable.rx_full.q),
-    .reg2hw_intr_test_q_i   (reg2hw.intr_test.rx_full.q  ),
-    .reg2hw_intr_test_qe_i  (reg2hw.intr_test.rx_full.qe ),
-    .reg2hw_intr_state_q_i  (reg2hw.intr_state.rx_full.q ),
-    .hw2reg_intr_state_de_o (hw2reg.intr_state.rx_full.de),
-    .hw2reg_intr_state_d_o  (hw2reg.intr_state.rx_full.d ),
-    .intr_o                 (intr_rx_full_o              )
+    .event_intr_i           (intr_sram_rxf_full                  ),
+    .reg2hw_intr_enable_q_i (reg2hw.intr_enable.generic_rx_full.q),
+    .reg2hw_intr_test_q_i   (reg2hw.intr_test.generic_rx_full.q  ),
+    .reg2hw_intr_test_qe_i  (reg2hw.intr_test.generic_rx_full.qe ),
+    .reg2hw_intr_state_q_i  (reg2hw.intr_state.generic_rx_full.q ),
+    .hw2reg_intr_state_de_o (hw2reg.intr_state.generic_rx_full.de),
+    .hw2reg_intr_state_d_o  (hw2reg.intr_state.generic_rx_full.d ),
+    .intr_o                 (intr_generic_rx_full_o              )
   );
 
   prim_intr_hw #(.Width(1)) u_intr_rxlvl (
     .clk_i,
     .rst_ni,
-    .event_intr_i           (intr_fwm_rxlvl                   ),
-    .reg2hw_intr_enable_q_i (reg2hw.intr_enable.rx_watermark.q),
-    .reg2hw_intr_test_q_i   (reg2hw.intr_test.rx_watermark.q  ),
-    .reg2hw_intr_test_qe_i  (reg2hw.intr_test.rx_watermark.qe ),
-    .reg2hw_intr_state_q_i  (reg2hw.intr_state.rx_watermark.q ),
-    .hw2reg_intr_state_de_o (hw2reg.intr_state.rx_watermark.de),
-    .hw2reg_intr_state_d_o  (hw2reg.intr_state.rx_watermark.d ),
-    .intr_o                 (intr_rx_watermark_o              )
+    .event_intr_i           (intr_fwm_rxlvl                           ),
+    .reg2hw_intr_enable_q_i (reg2hw.intr_enable.generic_rx_watermark.q),
+    .reg2hw_intr_test_q_i   (reg2hw.intr_test.generic_rx_watermark.q  ),
+    .reg2hw_intr_test_qe_i  (reg2hw.intr_test.generic_rx_watermark.qe ),
+    .reg2hw_intr_state_q_i  (reg2hw.intr_state.generic_rx_watermark.q ),
+    .hw2reg_intr_state_de_o (hw2reg.intr_state.generic_rx_watermark.de),
+    .hw2reg_intr_state_d_o  (hw2reg.intr_state.generic_rx_watermark.d ),
+    .intr_o                 (intr_generic_rx_watermark_o              )
   );
 
   prim_intr_hw #(.Width(1)) u_intr_txlvl (
     .clk_i,
     .rst_ni,
-    .event_intr_i           (intr_fwm_txlvl                   ),
-    .reg2hw_intr_enable_q_i (reg2hw.intr_enable.tx_watermark.q),
-    .reg2hw_intr_test_q_i   (reg2hw.intr_test.tx_watermark.q  ),
-    .reg2hw_intr_test_qe_i  (reg2hw.intr_test.tx_watermark.qe ),
-    .reg2hw_intr_state_q_i  (reg2hw.intr_state.tx_watermark.q ),
-    .hw2reg_intr_state_de_o (hw2reg.intr_state.tx_watermark.de),
-    .hw2reg_intr_state_d_o  (hw2reg.intr_state.tx_watermark.d ),
-    .intr_o                 (intr_tx_watermark_o              )
+    .event_intr_i           (intr_fwm_txlvl                           ),
+    .reg2hw_intr_enable_q_i (reg2hw.intr_enable.generic_tx_watermark.q),
+    .reg2hw_intr_test_q_i   (reg2hw.intr_test.generic_tx_watermark.q  ),
+    .reg2hw_intr_test_qe_i  (reg2hw.intr_test.generic_tx_watermark.qe ),
+    .reg2hw_intr_state_q_i  (reg2hw.intr_state.generic_tx_watermark.q ),
+    .hw2reg_intr_state_de_o (hw2reg.intr_state.generic_tx_watermark.de),
+    .hw2reg_intr_state_d_o  (hw2reg.intr_state.generic_tx_watermark.d ),
+    .intr_o                 (intr_generic_tx_watermark_o              )
   );
 
   prim_intr_hw #(.Width(1)) u_intr_rxerr (
     .clk_i,
     .rst_ni,
-    .event_intr_i           (intr_fwm_rxerr               ),
-    .reg2hw_intr_enable_q_i (reg2hw.intr_enable.rx_error.q),
-    .reg2hw_intr_test_q_i   (reg2hw.intr_test.rx_error.q  ),
-    .reg2hw_intr_test_qe_i  (reg2hw.intr_test.rx_error.qe ),
-    .reg2hw_intr_state_q_i  (reg2hw.intr_state.rx_error.q ),
-    .hw2reg_intr_state_de_o (hw2reg.intr_state.rx_error.de),
-    .hw2reg_intr_state_d_o  (hw2reg.intr_state.rx_error.d ),
-    .intr_o                 (intr_rx_error_o              )
+    .event_intr_i           (intr_fwm_rxerr                       ),
+    .reg2hw_intr_enable_q_i (reg2hw.intr_enable.generic_rx_error.q),
+    .reg2hw_intr_test_q_i   (reg2hw.intr_test.generic_rx_error.q  ),
+    .reg2hw_intr_test_qe_i  (reg2hw.intr_test.generic_rx_error.qe ),
+    .reg2hw_intr_state_q_i  (reg2hw.intr_state.generic_rx_error.q ),
+    .hw2reg_intr_state_de_o (hw2reg.intr_state.generic_rx_error.de),
+    .hw2reg_intr_state_d_o  (hw2reg.intr_state.generic_rx_error.d ),
+    .intr_o                 (intr_generic_rx_error_o              )
   );
 
   prim_intr_hw #(.Width(1)) u_intr_rxoverflow (
     .clk_i,
     .rst_ni,
-    .event_intr_i           (intr_fwm_rxoverflow             ),
-    .reg2hw_intr_enable_q_i (reg2hw.intr_enable.rx_overflow.q),
-    .reg2hw_intr_test_q_i   (reg2hw.intr_test.rx_overflow.q  ),
-    .reg2hw_intr_test_qe_i  (reg2hw.intr_test.rx_overflow.qe ),
-    .reg2hw_intr_state_q_i  (reg2hw.intr_state.rx_overflow.q ),
-    .hw2reg_intr_state_de_o (hw2reg.intr_state.rx_overflow.de),
-    .hw2reg_intr_state_d_o  (hw2reg.intr_state.rx_overflow.d ),
-    .intr_o                 (intr_rx_overflow_o              )
+    .event_intr_i           (intr_fwm_rxoverflow                     ),
+    .reg2hw_intr_enable_q_i (reg2hw.intr_enable.generic_rx_overflow.q),
+    .reg2hw_intr_test_q_i   (reg2hw.intr_test.generic_rx_overflow.q  ),
+    .reg2hw_intr_test_qe_i  (reg2hw.intr_test.generic_rx_overflow.qe ),
+    .reg2hw_intr_state_q_i  (reg2hw.intr_state.generic_rx_overflow.q ),
+    .hw2reg_intr_state_de_o (hw2reg.intr_state.generic_rx_overflow.de),
+    .hw2reg_intr_state_d_o  (hw2reg.intr_state.generic_rx_overflow.d ),
+    .intr_o                 (intr_generic_rx_overflow_o              )
   );
 
   prim_intr_hw #(.Width(1)) u_intr_txunderflow (
     .clk_i,
     .rst_ni,
-    .event_intr_i           (intr_fwm_txunderflow             ),
-    .reg2hw_intr_enable_q_i (reg2hw.intr_enable.tx_underflow.q),
-    .reg2hw_intr_test_q_i   (reg2hw.intr_test.tx_underflow.q  ),
-    .reg2hw_intr_test_qe_i  (reg2hw.intr_test.tx_underflow.qe ),
-    .reg2hw_intr_state_q_i  (reg2hw.intr_state.tx_underflow.q ),
-    .hw2reg_intr_state_de_o (hw2reg.intr_state.tx_underflow.de),
-    .hw2reg_intr_state_d_o  (hw2reg.intr_state.tx_underflow.d ),
-    .intr_o                 (intr_tx_underflow_o              )
+    .event_intr_i           (intr_fwm_txunderflow                     ),
+    .reg2hw_intr_enable_q_i (reg2hw.intr_enable.generic_tx_underflow.q),
+    .reg2hw_intr_test_q_i   (reg2hw.intr_test.generic_tx_underflow.q  ),
+    .reg2hw_intr_test_qe_i  (reg2hw.intr_test.generic_tx_underflow.qe ),
+    .reg2hw_intr_state_q_i  (reg2hw.intr_state.generic_tx_underflow.q ),
+    .hw2reg_intr_state_de_o (hw2reg.intr_state.generic_tx_underflow.de),
+    .hw2reg_intr_state_d_o  (hw2reg.intr_state.generic_tx_underflow.d ),
+    .intr_o                 (intr_generic_tx_underflow_o              )
   );
 
   prim_edge_detector #(
@@ -564,27 +564,27 @@
   prim_intr_hw #(.Width(1)) u_intr_cmdfifo_not_empty (
     .clk_i,
     .rst_ni,
-    .event_intr_i           (intr_upload_cmdfifo_not_empty         ),
-    .reg2hw_intr_enable_q_i (reg2hw.intr_enable.cmdfifo_not_empty.q),
-    .reg2hw_intr_test_q_i   (reg2hw.intr_test.cmdfifo_not_empty.q  ),
-    .reg2hw_intr_test_qe_i  (reg2hw.intr_test.cmdfifo_not_empty.qe ),
-    .reg2hw_intr_state_q_i  (reg2hw.intr_state.cmdfifo_not_empty.q ),
-    .hw2reg_intr_state_d_o  (hw2reg.intr_state.cmdfifo_not_empty.d ),
-    .hw2reg_intr_state_de_o (hw2reg.intr_state.cmdfifo_not_empty.de),
-    .intr_o                 (intr_cmdfifo_not_empty_o              )
+    .event_intr_i           (intr_upload_cmdfifo_not_empty                ),
+    .reg2hw_intr_enable_q_i (reg2hw.intr_enable.upload_cmdfifo_not_empty.q),
+    .reg2hw_intr_test_q_i   (reg2hw.intr_test.upload_cmdfifo_not_empty.q  ),
+    .reg2hw_intr_test_qe_i  (reg2hw.intr_test.upload_cmdfifo_not_empty.qe ),
+    .reg2hw_intr_state_q_i  (reg2hw.intr_state.upload_cmdfifo_not_empty.q ),
+    .hw2reg_intr_state_d_o  (hw2reg.intr_state.upload_cmdfifo_not_empty.d ),
+    .hw2reg_intr_state_de_o (hw2reg.intr_state.upload_cmdfifo_not_empty.de),
+    .intr_o                 (intr_upload_cmdfifo_not_empty_o              )
   );
 
   prim_intr_hw #(.Width(1)) u_intr_payload_not_empty (
     .clk_i,
     .rst_ni,
-    .event_intr_i           (intr_upload_payload_not_empty         ),
-    .reg2hw_intr_enable_q_i (reg2hw.intr_enable.payload_not_empty.q),
-    .reg2hw_intr_test_q_i   (reg2hw.intr_test.payload_not_empty.q  ),
-    .reg2hw_intr_test_qe_i  (reg2hw.intr_test.payload_not_empty.qe ),
-    .reg2hw_intr_state_q_i  (reg2hw.intr_state.payload_not_empty.q ),
-    .hw2reg_intr_state_d_o  (hw2reg.intr_state.payload_not_empty.d ),
-    .hw2reg_intr_state_de_o (hw2reg.intr_state.payload_not_empty.de),
-    .intr_o                 (intr_payload_not_empty_o              )
+    .event_intr_i           (intr_upload_payload_not_empty                ),
+    .reg2hw_intr_enable_q_i (reg2hw.intr_enable.upload_payload_not_empty.q),
+    .reg2hw_intr_test_q_i   (reg2hw.intr_test.upload_payload_not_empty.q  ),
+    .reg2hw_intr_test_qe_i  (reg2hw.intr_test.upload_payload_not_empty.qe ),
+    .reg2hw_intr_state_q_i  (reg2hw.intr_state.upload_payload_not_empty.q ),
+    .hw2reg_intr_state_d_o  (hw2reg.intr_state.upload_payload_not_empty.d ),
+    .hw2reg_intr_state_de_o (hw2reg.intr_state.upload_payload_not_empty.de),
+    .intr_o                 (intr_upload_payload_not_empty_o              )
   );
 
   prim_intr_hw #(.Width(1)) u_intr_readbuf_watermark (
@@ -1777,12 +1777,18 @@
   `ASSERT_KNOWN(scanmodeKnown, scanmode_i, clk_i, 0)
   `ASSERT_KNOWN(CioSdoEnOKnown, cio_sd_en_o)
 
-  `ASSERT_KNOWN(IntrRxfOKnown,         intr_rx_full_o     )
-  `ASSERT_KNOWN(IntrRxlvlOKnown,       intr_rx_watermark_o)
-  `ASSERT_KNOWN(IntrTxlvlOKnown,       intr_tx_watermark_o)
-  `ASSERT_KNOWN(IntrRxerrOKnown,       intr_rx_error_o    )
-  `ASSERT_KNOWN(IntrRxoverflowOKnown,  intr_rx_overflow_o )
-  `ASSERT_KNOWN(IntrTxunderflowOKnown, intr_tx_underflow_o)
+  `ASSERT_KNOWN(IntrRxfOKnown,         intr_generic_rx_full_o     )
+  `ASSERT_KNOWN(IntrRxlvlOKnown,       intr_generic_rx_watermark_o)
+  `ASSERT_KNOWN(IntrTxlvlOKnown,       intr_generic_tx_watermark_o)
+  `ASSERT_KNOWN(IntrRxerrOKnown,       intr_generic_rx_error_o    )
+  `ASSERT_KNOWN(IntrRxoverflowOKnown,  intr_generic_rx_overflow_o )
+  `ASSERT_KNOWN(IntrTxunderflowOKnown, intr_generic_tx_underflow_o)
+  `ASSERT_KNOWN(IntrUploadCmdfifoNotEmptyOKnown,
+                intr_upload_cmdfifo_not_empty_o)
+  `ASSERT_KNOWN(IntrUploadPayloadNotEmptyOKnown,
+                intr_upload_payload_not_empty_o)
+  `ASSERT_KNOWN(IntrReadbufWatermarkOKnown,  intr_readbuf_watermark_o)
+  `ASSERT_KNOWN(IntrReadbufFlipOKnown,       intr_readbuf_flip_o)
   `ASSERT_KNOWN(IntrTpmHeaderNotEmptyOKnown, intr_tpm_header_not_empty_o)
 
   `ASSERT_KNOWN(AlertKnownO_A,         alert_tx_o)
diff --git a/hw/ip/spi_device/rtl/spi_device_reg_pkg.sv b/hw/ip/spi_device/rtl/spi_device_reg_pkg.sv
index 04c5435..be2fa88 100644
--- a/hw/ip/spi_device/rtl/spi_device_reg_pkg.sv
+++ b/hw/ip/spi_device/rtl/spi_device_reg_pkg.sv
@@ -22,28 +22,28 @@
   typedef struct packed {
     struct packed {
       logic        q;
-    } rx_full;
+    } generic_rx_full;
     struct packed {
       logic        q;
-    } rx_watermark;
+    } generic_rx_watermark;
     struct packed {
       logic        q;
-    } tx_watermark;
+    } generic_tx_watermark;
     struct packed {
       logic        q;
-    } rx_error;
+    } generic_rx_error;
     struct packed {
       logic        q;
-    } rx_overflow;
+    } generic_rx_overflow;
     struct packed {
       logic        q;
-    } tx_underflow;
+    } generic_tx_underflow;
     struct packed {
       logic        q;
-    } cmdfifo_not_empty;
+    } upload_cmdfifo_not_empty;
     struct packed {
       logic        q;
-    } payload_not_empty;
+    } upload_payload_not_empty;
     struct packed {
       logic        q;
     } readbuf_watermark;
@@ -58,28 +58,28 @@
   typedef struct packed {
     struct packed {
       logic        q;
-    } rx_full;
+    } generic_rx_full;
     struct packed {
       logic        q;
-    } rx_watermark;
+    } generic_rx_watermark;
     struct packed {
       logic        q;
-    } tx_watermark;
+    } generic_tx_watermark;
     struct packed {
       logic        q;
-    } rx_error;
+    } generic_rx_error;
     struct packed {
       logic        q;
-    } rx_overflow;
+    } generic_rx_overflow;
     struct packed {
       logic        q;
-    } tx_underflow;
+    } generic_tx_underflow;
     struct packed {
       logic        q;
-    } cmdfifo_not_empty;
+    } upload_cmdfifo_not_empty;
     struct packed {
       logic        q;
-    } payload_not_empty;
+    } upload_payload_not_empty;
     struct packed {
       logic        q;
     } readbuf_watermark;
@@ -95,35 +95,35 @@
     struct packed {
       logic        q;
       logic        qe;
-    } rx_full;
+    } generic_rx_full;
     struct packed {
       logic        q;
       logic        qe;
-    } rx_watermark;
+    } generic_rx_watermark;
     struct packed {
       logic        q;
       logic        qe;
-    } tx_watermark;
+    } generic_tx_watermark;
     struct packed {
       logic        q;
       logic        qe;
-    } rx_error;
+    } generic_rx_error;
     struct packed {
       logic        q;
       logic        qe;
-    } rx_overflow;
+    } generic_rx_overflow;
     struct packed {
       logic        q;
       logic        qe;
-    } tx_underflow;
+    } generic_tx_underflow;
     struct packed {
       logic        q;
       logic        qe;
-    } cmdfifo_not_empty;
+    } upload_cmdfifo_not_empty;
     struct packed {
       logic        q;
       logic        qe;
-    } payload_not_empty;
+    } upload_payload_not_empty;
     struct packed {
       logic        q;
       logic        qe;
@@ -419,35 +419,35 @@
     struct packed {
       logic        d;
       logic        de;
-    } rx_full;
+    } generic_rx_full;
     struct packed {
       logic        d;
       logic        de;
-    } rx_watermark;
+    } generic_rx_watermark;
     struct packed {
       logic        d;
       logic        de;
-    } tx_watermark;
+    } generic_tx_watermark;
     struct packed {
       logic        d;
       logic        de;
-    } rx_error;
+    } generic_rx_error;
     struct packed {
       logic        d;
       logic        de;
-    } rx_overflow;
+    } generic_rx_overflow;
     struct packed {
       logic        d;
       logic        de;
-    } tx_underflow;
+    } generic_tx_underflow;
     struct packed {
       logic        d;
       logic        de;
-    } cmdfifo_not_empty;
+    } upload_cmdfifo_not_empty;
     struct packed {
       logic        d;
       logic        de;
-    } payload_not_empty;
+    } upload_payload_not_empty;
     struct packed {
       logic        d;
       logic        de;
@@ -732,14 +732,14 @@
 
   // Reset values for hwext registers and their fields
   parameter logic [10:0] SPI_DEVICE_INTR_TEST_RESVAL = 11'h 0;
-  parameter logic [0:0] SPI_DEVICE_INTR_TEST_RX_FULL_RESVAL = 1'h 0;
-  parameter logic [0:0] SPI_DEVICE_INTR_TEST_RX_WATERMARK_RESVAL = 1'h 0;
-  parameter logic [0:0] SPI_DEVICE_INTR_TEST_TX_WATERMARK_RESVAL = 1'h 0;
-  parameter logic [0:0] SPI_DEVICE_INTR_TEST_RX_ERROR_RESVAL = 1'h 0;
-  parameter logic [0:0] SPI_DEVICE_INTR_TEST_RX_OVERFLOW_RESVAL = 1'h 0;
-  parameter logic [0:0] SPI_DEVICE_INTR_TEST_TX_UNDERFLOW_RESVAL = 1'h 0;
-  parameter logic [0:0] SPI_DEVICE_INTR_TEST_CMDFIFO_NOT_EMPTY_RESVAL = 1'h 0;
-  parameter logic [0:0] SPI_DEVICE_INTR_TEST_PAYLOAD_NOT_EMPTY_RESVAL = 1'h 0;
+  parameter logic [0:0] SPI_DEVICE_INTR_TEST_GENERIC_RX_FULL_RESVAL = 1'h 0;
+  parameter logic [0:0] SPI_DEVICE_INTR_TEST_GENERIC_RX_WATERMARK_RESVAL = 1'h 0;
+  parameter logic [0:0] SPI_DEVICE_INTR_TEST_GENERIC_TX_WATERMARK_RESVAL = 1'h 0;
+  parameter logic [0:0] SPI_DEVICE_INTR_TEST_GENERIC_RX_ERROR_RESVAL = 1'h 0;
+  parameter logic [0:0] SPI_DEVICE_INTR_TEST_GENERIC_RX_OVERFLOW_RESVAL = 1'h 0;
+  parameter logic [0:0] SPI_DEVICE_INTR_TEST_GENERIC_TX_UNDERFLOW_RESVAL = 1'h 0;
+  parameter logic [0:0] SPI_DEVICE_INTR_TEST_UPLOAD_CMDFIFO_NOT_EMPTY_RESVAL = 1'h 0;
+  parameter logic [0:0] SPI_DEVICE_INTR_TEST_UPLOAD_PAYLOAD_NOT_EMPTY_RESVAL = 1'h 0;
   parameter logic [0:0] SPI_DEVICE_INTR_TEST_READBUF_WATERMARK_RESVAL = 1'h 0;
   parameter logic [0:0] SPI_DEVICE_INTR_TEST_READBUF_FLIP_RESVAL = 1'h 0;
   parameter logic [0:0] SPI_DEVICE_INTR_TEST_TPM_HEADER_NOT_EMPTY_RESVAL = 1'h 0;
diff --git a/hw/ip/spi_device/rtl/spi_device_reg_top.sv b/hw/ip/spi_device/rtl/spi_device_reg_top.sv
index be66dea..143412f 100644
--- a/hw/ip/spi_device/rtl/spi_device_reg_top.sv
+++ b/hw/ip/spi_device/rtl/spi_device_reg_top.sv
@@ -157,22 +157,22 @@
   // Format: <reg>_<field>_{wd|we|qs}
   //        or <reg>_{wd|we|qs} if field == 1 or 0
   logic intr_state_we;
-  logic intr_state_rx_full_qs;
-  logic intr_state_rx_full_wd;
-  logic intr_state_rx_watermark_qs;
-  logic intr_state_rx_watermark_wd;
-  logic intr_state_tx_watermark_qs;
-  logic intr_state_tx_watermark_wd;
-  logic intr_state_rx_error_qs;
-  logic intr_state_rx_error_wd;
-  logic intr_state_rx_overflow_qs;
-  logic intr_state_rx_overflow_wd;
-  logic intr_state_tx_underflow_qs;
-  logic intr_state_tx_underflow_wd;
-  logic intr_state_cmdfifo_not_empty_qs;
-  logic intr_state_cmdfifo_not_empty_wd;
-  logic intr_state_payload_not_empty_qs;
-  logic intr_state_payload_not_empty_wd;
+  logic intr_state_generic_rx_full_qs;
+  logic intr_state_generic_rx_full_wd;
+  logic intr_state_generic_rx_watermark_qs;
+  logic intr_state_generic_rx_watermark_wd;
+  logic intr_state_generic_tx_watermark_qs;
+  logic intr_state_generic_tx_watermark_wd;
+  logic intr_state_generic_rx_error_qs;
+  logic intr_state_generic_rx_error_wd;
+  logic intr_state_generic_rx_overflow_qs;
+  logic intr_state_generic_rx_overflow_wd;
+  logic intr_state_generic_tx_underflow_qs;
+  logic intr_state_generic_tx_underflow_wd;
+  logic intr_state_upload_cmdfifo_not_empty_qs;
+  logic intr_state_upload_cmdfifo_not_empty_wd;
+  logic intr_state_upload_payload_not_empty_qs;
+  logic intr_state_upload_payload_not_empty_wd;
   logic intr_state_readbuf_watermark_qs;
   logic intr_state_readbuf_watermark_wd;
   logic intr_state_readbuf_flip_qs;
@@ -180,22 +180,22 @@
   logic intr_state_tpm_header_not_empty_qs;
   logic intr_state_tpm_header_not_empty_wd;
   logic intr_enable_we;
-  logic intr_enable_rx_full_qs;
-  logic intr_enable_rx_full_wd;
-  logic intr_enable_rx_watermark_qs;
-  logic intr_enable_rx_watermark_wd;
-  logic intr_enable_tx_watermark_qs;
-  logic intr_enable_tx_watermark_wd;
-  logic intr_enable_rx_error_qs;
-  logic intr_enable_rx_error_wd;
-  logic intr_enable_rx_overflow_qs;
-  logic intr_enable_rx_overflow_wd;
-  logic intr_enable_tx_underflow_qs;
-  logic intr_enable_tx_underflow_wd;
-  logic intr_enable_cmdfifo_not_empty_qs;
-  logic intr_enable_cmdfifo_not_empty_wd;
-  logic intr_enable_payload_not_empty_qs;
-  logic intr_enable_payload_not_empty_wd;
+  logic intr_enable_generic_rx_full_qs;
+  logic intr_enable_generic_rx_full_wd;
+  logic intr_enable_generic_rx_watermark_qs;
+  logic intr_enable_generic_rx_watermark_wd;
+  logic intr_enable_generic_tx_watermark_qs;
+  logic intr_enable_generic_tx_watermark_wd;
+  logic intr_enable_generic_rx_error_qs;
+  logic intr_enable_generic_rx_error_wd;
+  logic intr_enable_generic_rx_overflow_qs;
+  logic intr_enable_generic_rx_overflow_wd;
+  logic intr_enable_generic_tx_underflow_qs;
+  logic intr_enable_generic_tx_underflow_wd;
+  logic intr_enable_upload_cmdfifo_not_empty_qs;
+  logic intr_enable_upload_cmdfifo_not_empty_wd;
+  logic intr_enable_upload_payload_not_empty_qs;
+  logic intr_enable_upload_payload_not_empty_wd;
   logic intr_enable_readbuf_watermark_qs;
   logic intr_enable_readbuf_watermark_wd;
   logic intr_enable_readbuf_flip_qs;
@@ -203,14 +203,14 @@
   logic intr_enable_tpm_header_not_empty_qs;
   logic intr_enable_tpm_header_not_empty_wd;
   logic intr_test_we;
-  logic intr_test_rx_full_wd;
-  logic intr_test_rx_watermark_wd;
-  logic intr_test_tx_watermark_wd;
-  logic intr_test_rx_error_wd;
-  logic intr_test_rx_overflow_wd;
-  logic intr_test_tx_underflow_wd;
-  logic intr_test_cmdfifo_not_empty_wd;
-  logic intr_test_payload_not_empty_wd;
+  logic intr_test_generic_rx_full_wd;
+  logic intr_test_generic_rx_watermark_wd;
+  logic intr_test_generic_tx_watermark_wd;
+  logic intr_test_generic_rx_error_wd;
+  logic intr_test_generic_rx_overflow_wd;
+  logic intr_test_generic_tx_underflow_wd;
+  logic intr_test_upload_cmdfifo_not_empty_wd;
+  logic intr_test_upload_payload_not_empty_wd;
   logic intr_test_readbuf_watermark_wd;
   logic intr_test_readbuf_flip_wd;
   logic intr_test_tpm_header_not_empty_wd;
@@ -1507,204 +1507,204 @@
 
   // Register instances
   // R[intr_state]: V(False)
-  //   F[rx_full]: 0:0
+  //   F[generic_rx_full]: 0:0
   prim_subreg #(
     .DW      (1),
     .SwAccess(prim_subreg_pkg::SwAccessW1C),
     .RESVAL  (1'h0)
-  ) u_intr_state_rx_full (
+  ) u_intr_state_generic_rx_full (
     .clk_i   (clk_i),
     .rst_ni  (rst_ni),
 
     // from register interface
     .we     (intr_state_we),
-    .wd     (intr_state_rx_full_wd),
+    .wd     (intr_state_generic_rx_full_wd),
 
     // from internal hardware
-    .de     (hw2reg.intr_state.rx_full.de),
-    .d      (hw2reg.intr_state.rx_full.d),
+    .de     (hw2reg.intr_state.generic_rx_full.de),
+    .d      (hw2reg.intr_state.generic_rx_full.d),
 
     // to internal hardware
     .qe     (),
-    .q      (reg2hw.intr_state.rx_full.q),
+    .q      (reg2hw.intr_state.generic_rx_full.q),
 
     // to register interface (read)
-    .qs     (intr_state_rx_full_qs)
+    .qs     (intr_state_generic_rx_full_qs)
   );
 
-  //   F[rx_watermark]: 1:1
+  //   F[generic_rx_watermark]: 1:1
   prim_subreg #(
     .DW      (1),
     .SwAccess(prim_subreg_pkg::SwAccessW1C),
     .RESVAL  (1'h0)
-  ) u_intr_state_rx_watermark (
+  ) u_intr_state_generic_rx_watermark (
     .clk_i   (clk_i),
     .rst_ni  (rst_ni),
 
     // from register interface
     .we     (intr_state_we),
-    .wd     (intr_state_rx_watermark_wd),
+    .wd     (intr_state_generic_rx_watermark_wd),
 
     // from internal hardware
-    .de     (hw2reg.intr_state.rx_watermark.de),
-    .d      (hw2reg.intr_state.rx_watermark.d),
+    .de     (hw2reg.intr_state.generic_rx_watermark.de),
+    .d      (hw2reg.intr_state.generic_rx_watermark.d),
 
     // to internal hardware
     .qe     (),
-    .q      (reg2hw.intr_state.rx_watermark.q),
+    .q      (reg2hw.intr_state.generic_rx_watermark.q),
 
     // to register interface (read)
-    .qs     (intr_state_rx_watermark_qs)
+    .qs     (intr_state_generic_rx_watermark_qs)
   );
 
-  //   F[tx_watermark]: 2:2
+  //   F[generic_tx_watermark]: 2:2
   prim_subreg #(
     .DW      (1),
     .SwAccess(prim_subreg_pkg::SwAccessW1C),
     .RESVAL  (1'h0)
-  ) u_intr_state_tx_watermark (
+  ) u_intr_state_generic_tx_watermark (
     .clk_i   (clk_i),
     .rst_ni  (rst_ni),
 
     // from register interface
     .we     (intr_state_we),
-    .wd     (intr_state_tx_watermark_wd),
+    .wd     (intr_state_generic_tx_watermark_wd),
 
     // from internal hardware
-    .de     (hw2reg.intr_state.tx_watermark.de),
-    .d      (hw2reg.intr_state.tx_watermark.d),
+    .de     (hw2reg.intr_state.generic_tx_watermark.de),
+    .d      (hw2reg.intr_state.generic_tx_watermark.d),
 
     // to internal hardware
     .qe     (),
-    .q      (reg2hw.intr_state.tx_watermark.q),
+    .q      (reg2hw.intr_state.generic_tx_watermark.q),
 
     // to register interface (read)
-    .qs     (intr_state_tx_watermark_qs)
+    .qs     (intr_state_generic_tx_watermark_qs)
   );
 
-  //   F[rx_error]: 3:3
+  //   F[generic_rx_error]: 3:3
   prim_subreg #(
     .DW      (1),
     .SwAccess(prim_subreg_pkg::SwAccessW1C),
     .RESVAL  (1'h0)
-  ) u_intr_state_rx_error (
+  ) u_intr_state_generic_rx_error (
     .clk_i   (clk_i),
     .rst_ni  (rst_ni),
 
     // from register interface
     .we     (intr_state_we),
-    .wd     (intr_state_rx_error_wd),
+    .wd     (intr_state_generic_rx_error_wd),
 
     // from internal hardware
-    .de     (hw2reg.intr_state.rx_error.de),
-    .d      (hw2reg.intr_state.rx_error.d),
+    .de     (hw2reg.intr_state.generic_rx_error.de),
+    .d      (hw2reg.intr_state.generic_rx_error.d),
 
     // to internal hardware
     .qe     (),
-    .q      (reg2hw.intr_state.rx_error.q),
+    .q      (reg2hw.intr_state.generic_rx_error.q),
 
     // to register interface (read)
-    .qs     (intr_state_rx_error_qs)
+    .qs     (intr_state_generic_rx_error_qs)
   );
 
-  //   F[rx_overflow]: 4:4
+  //   F[generic_rx_overflow]: 4:4
   prim_subreg #(
     .DW      (1),
     .SwAccess(prim_subreg_pkg::SwAccessW1C),
     .RESVAL  (1'h0)
-  ) u_intr_state_rx_overflow (
+  ) u_intr_state_generic_rx_overflow (
     .clk_i   (clk_i),
     .rst_ni  (rst_ni),
 
     // from register interface
     .we     (intr_state_we),
-    .wd     (intr_state_rx_overflow_wd),
+    .wd     (intr_state_generic_rx_overflow_wd),
 
     // from internal hardware
-    .de     (hw2reg.intr_state.rx_overflow.de),
-    .d      (hw2reg.intr_state.rx_overflow.d),
+    .de     (hw2reg.intr_state.generic_rx_overflow.de),
+    .d      (hw2reg.intr_state.generic_rx_overflow.d),
 
     // to internal hardware
     .qe     (),
-    .q      (reg2hw.intr_state.rx_overflow.q),
+    .q      (reg2hw.intr_state.generic_rx_overflow.q),
 
     // to register interface (read)
-    .qs     (intr_state_rx_overflow_qs)
+    .qs     (intr_state_generic_rx_overflow_qs)
   );
 
-  //   F[tx_underflow]: 5:5
+  //   F[generic_tx_underflow]: 5:5
   prim_subreg #(
     .DW      (1),
     .SwAccess(prim_subreg_pkg::SwAccessW1C),
     .RESVAL  (1'h0)
-  ) u_intr_state_tx_underflow (
+  ) u_intr_state_generic_tx_underflow (
     .clk_i   (clk_i),
     .rst_ni  (rst_ni),
 
     // from register interface
     .we     (intr_state_we),
-    .wd     (intr_state_tx_underflow_wd),
+    .wd     (intr_state_generic_tx_underflow_wd),
 
     // from internal hardware
-    .de     (hw2reg.intr_state.tx_underflow.de),
-    .d      (hw2reg.intr_state.tx_underflow.d),
+    .de     (hw2reg.intr_state.generic_tx_underflow.de),
+    .d      (hw2reg.intr_state.generic_tx_underflow.d),
 
     // to internal hardware
     .qe     (),
-    .q      (reg2hw.intr_state.tx_underflow.q),
+    .q      (reg2hw.intr_state.generic_tx_underflow.q),
 
     // to register interface (read)
-    .qs     (intr_state_tx_underflow_qs)
+    .qs     (intr_state_generic_tx_underflow_qs)
   );
 
-  //   F[cmdfifo_not_empty]: 6:6
+  //   F[upload_cmdfifo_not_empty]: 6:6
   prim_subreg #(
     .DW      (1),
     .SwAccess(prim_subreg_pkg::SwAccessW1C),
     .RESVAL  (1'h0)
-  ) u_intr_state_cmdfifo_not_empty (
+  ) u_intr_state_upload_cmdfifo_not_empty (
     .clk_i   (clk_i),
     .rst_ni  (rst_ni),
 
     // from register interface
     .we     (intr_state_we),
-    .wd     (intr_state_cmdfifo_not_empty_wd),
+    .wd     (intr_state_upload_cmdfifo_not_empty_wd),
 
     // from internal hardware
-    .de     (hw2reg.intr_state.cmdfifo_not_empty.de),
-    .d      (hw2reg.intr_state.cmdfifo_not_empty.d),
+    .de     (hw2reg.intr_state.upload_cmdfifo_not_empty.de),
+    .d      (hw2reg.intr_state.upload_cmdfifo_not_empty.d),
 
     // to internal hardware
     .qe     (),
-    .q      (reg2hw.intr_state.cmdfifo_not_empty.q),
+    .q      (reg2hw.intr_state.upload_cmdfifo_not_empty.q),
 
     // to register interface (read)
-    .qs     (intr_state_cmdfifo_not_empty_qs)
+    .qs     (intr_state_upload_cmdfifo_not_empty_qs)
   );
 
-  //   F[payload_not_empty]: 7:7
+  //   F[upload_payload_not_empty]: 7:7
   prim_subreg #(
     .DW      (1),
     .SwAccess(prim_subreg_pkg::SwAccessW1C),
     .RESVAL  (1'h0)
-  ) u_intr_state_payload_not_empty (
+  ) u_intr_state_upload_payload_not_empty (
     .clk_i   (clk_i),
     .rst_ni  (rst_ni),
 
     // from register interface
     .we     (intr_state_we),
-    .wd     (intr_state_payload_not_empty_wd),
+    .wd     (intr_state_upload_payload_not_empty_wd),
 
     // from internal hardware
-    .de     (hw2reg.intr_state.payload_not_empty.de),
-    .d      (hw2reg.intr_state.payload_not_empty.d),
+    .de     (hw2reg.intr_state.upload_payload_not_empty.de),
+    .d      (hw2reg.intr_state.upload_payload_not_empty.d),
 
     // to internal hardware
     .qe     (),
-    .q      (reg2hw.intr_state.payload_not_empty.q),
+    .q      (reg2hw.intr_state.upload_payload_not_empty.q),
 
     // to register interface (read)
-    .qs     (intr_state_payload_not_empty_qs)
+    .qs     (intr_state_upload_payload_not_empty_qs)
   );
 
   //   F[readbuf_watermark]: 8:8
@@ -1784,18 +1784,18 @@
 
 
   // R[intr_enable]: V(False)
-  //   F[rx_full]: 0:0
+  //   F[generic_rx_full]: 0:0
   prim_subreg #(
     .DW      (1),
     .SwAccess(prim_subreg_pkg::SwAccessRW),
     .RESVAL  (1'h0)
-  ) u_intr_enable_rx_full (
+  ) u_intr_enable_generic_rx_full (
     .clk_i   (clk_i),
     .rst_ni  (rst_ni),
 
     // from register interface
     .we     (intr_enable_we),
-    .wd     (intr_enable_rx_full_wd),
+    .wd     (intr_enable_generic_rx_full_wd),
 
     // from internal hardware
     .de     (1'b0),
@@ -1803,24 +1803,24 @@
 
     // to internal hardware
     .qe     (),
-    .q      (reg2hw.intr_enable.rx_full.q),
+    .q      (reg2hw.intr_enable.generic_rx_full.q),
 
     // to register interface (read)
-    .qs     (intr_enable_rx_full_qs)
+    .qs     (intr_enable_generic_rx_full_qs)
   );
 
-  //   F[rx_watermark]: 1:1
+  //   F[generic_rx_watermark]: 1:1
   prim_subreg #(
     .DW      (1),
     .SwAccess(prim_subreg_pkg::SwAccessRW),
     .RESVAL  (1'h0)
-  ) u_intr_enable_rx_watermark (
+  ) u_intr_enable_generic_rx_watermark (
     .clk_i   (clk_i),
     .rst_ni  (rst_ni),
 
     // from register interface
     .we     (intr_enable_we),
-    .wd     (intr_enable_rx_watermark_wd),
+    .wd     (intr_enable_generic_rx_watermark_wd),
 
     // from internal hardware
     .de     (1'b0),
@@ -1828,24 +1828,24 @@
 
     // to internal hardware
     .qe     (),
-    .q      (reg2hw.intr_enable.rx_watermark.q),
+    .q      (reg2hw.intr_enable.generic_rx_watermark.q),
 
     // to register interface (read)
-    .qs     (intr_enable_rx_watermark_qs)
+    .qs     (intr_enable_generic_rx_watermark_qs)
   );
 
-  //   F[tx_watermark]: 2:2
+  //   F[generic_tx_watermark]: 2:2
   prim_subreg #(
     .DW      (1),
     .SwAccess(prim_subreg_pkg::SwAccessRW),
     .RESVAL  (1'h0)
-  ) u_intr_enable_tx_watermark (
+  ) u_intr_enable_generic_tx_watermark (
     .clk_i   (clk_i),
     .rst_ni  (rst_ni),
 
     // from register interface
     .we     (intr_enable_we),
-    .wd     (intr_enable_tx_watermark_wd),
+    .wd     (intr_enable_generic_tx_watermark_wd),
 
     // from internal hardware
     .de     (1'b0),
@@ -1853,24 +1853,24 @@
 
     // to internal hardware
     .qe     (),
-    .q      (reg2hw.intr_enable.tx_watermark.q),
+    .q      (reg2hw.intr_enable.generic_tx_watermark.q),
 
     // to register interface (read)
-    .qs     (intr_enable_tx_watermark_qs)
+    .qs     (intr_enable_generic_tx_watermark_qs)
   );
 
-  //   F[rx_error]: 3:3
+  //   F[generic_rx_error]: 3:3
   prim_subreg #(
     .DW      (1),
     .SwAccess(prim_subreg_pkg::SwAccessRW),
     .RESVAL  (1'h0)
-  ) u_intr_enable_rx_error (
+  ) u_intr_enable_generic_rx_error (
     .clk_i   (clk_i),
     .rst_ni  (rst_ni),
 
     // from register interface
     .we     (intr_enable_we),
-    .wd     (intr_enable_rx_error_wd),
+    .wd     (intr_enable_generic_rx_error_wd),
 
     // from internal hardware
     .de     (1'b0),
@@ -1878,24 +1878,24 @@
 
     // to internal hardware
     .qe     (),
-    .q      (reg2hw.intr_enable.rx_error.q),
+    .q      (reg2hw.intr_enable.generic_rx_error.q),
 
     // to register interface (read)
-    .qs     (intr_enable_rx_error_qs)
+    .qs     (intr_enable_generic_rx_error_qs)
   );
 
-  //   F[rx_overflow]: 4:4
+  //   F[generic_rx_overflow]: 4:4
   prim_subreg #(
     .DW      (1),
     .SwAccess(prim_subreg_pkg::SwAccessRW),
     .RESVAL  (1'h0)
-  ) u_intr_enable_rx_overflow (
+  ) u_intr_enable_generic_rx_overflow (
     .clk_i   (clk_i),
     .rst_ni  (rst_ni),
 
     // from register interface
     .we     (intr_enable_we),
-    .wd     (intr_enable_rx_overflow_wd),
+    .wd     (intr_enable_generic_rx_overflow_wd),
 
     // from internal hardware
     .de     (1'b0),
@@ -1903,24 +1903,24 @@
 
     // to internal hardware
     .qe     (),
-    .q      (reg2hw.intr_enable.rx_overflow.q),
+    .q      (reg2hw.intr_enable.generic_rx_overflow.q),
 
     // to register interface (read)
-    .qs     (intr_enable_rx_overflow_qs)
+    .qs     (intr_enable_generic_rx_overflow_qs)
   );
 
-  //   F[tx_underflow]: 5:5
+  //   F[generic_tx_underflow]: 5:5
   prim_subreg #(
     .DW      (1),
     .SwAccess(prim_subreg_pkg::SwAccessRW),
     .RESVAL  (1'h0)
-  ) u_intr_enable_tx_underflow (
+  ) u_intr_enable_generic_tx_underflow (
     .clk_i   (clk_i),
     .rst_ni  (rst_ni),
 
     // from register interface
     .we     (intr_enable_we),
-    .wd     (intr_enable_tx_underflow_wd),
+    .wd     (intr_enable_generic_tx_underflow_wd),
 
     // from internal hardware
     .de     (1'b0),
@@ -1928,24 +1928,24 @@
 
     // to internal hardware
     .qe     (),
-    .q      (reg2hw.intr_enable.tx_underflow.q),
+    .q      (reg2hw.intr_enable.generic_tx_underflow.q),
 
     // to register interface (read)
-    .qs     (intr_enable_tx_underflow_qs)
+    .qs     (intr_enable_generic_tx_underflow_qs)
   );
 
-  //   F[cmdfifo_not_empty]: 6:6
+  //   F[upload_cmdfifo_not_empty]: 6:6
   prim_subreg #(
     .DW      (1),
     .SwAccess(prim_subreg_pkg::SwAccessRW),
     .RESVAL  (1'h0)
-  ) u_intr_enable_cmdfifo_not_empty (
+  ) u_intr_enable_upload_cmdfifo_not_empty (
     .clk_i   (clk_i),
     .rst_ni  (rst_ni),
 
     // from register interface
     .we     (intr_enable_we),
-    .wd     (intr_enable_cmdfifo_not_empty_wd),
+    .wd     (intr_enable_upload_cmdfifo_not_empty_wd),
 
     // from internal hardware
     .de     (1'b0),
@@ -1953,24 +1953,24 @@
 
     // to internal hardware
     .qe     (),
-    .q      (reg2hw.intr_enable.cmdfifo_not_empty.q),
+    .q      (reg2hw.intr_enable.upload_cmdfifo_not_empty.q),
 
     // to register interface (read)
-    .qs     (intr_enable_cmdfifo_not_empty_qs)
+    .qs     (intr_enable_upload_cmdfifo_not_empty_qs)
   );
 
-  //   F[payload_not_empty]: 7:7
+  //   F[upload_payload_not_empty]: 7:7
   prim_subreg #(
     .DW      (1),
     .SwAccess(prim_subreg_pkg::SwAccessRW),
     .RESVAL  (1'h0)
-  ) u_intr_enable_payload_not_empty (
+  ) u_intr_enable_upload_payload_not_empty (
     .clk_i   (clk_i),
     .rst_ni  (rst_ni),
 
     // from register interface
     .we     (intr_enable_we),
-    .wd     (intr_enable_payload_not_empty_wd),
+    .wd     (intr_enable_upload_payload_not_empty_wd),
 
     // from internal hardware
     .de     (1'b0),
@@ -1978,10 +1978,10 @@
 
     // to internal hardware
     .qe     (),
-    .q      (reg2hw.intr_enable.payload_not_empty.q),
+    .q      (reg2hw.intr_enable.upload_payload_not_empty.q),
 
     // to register interface (read)
-    .qs     (intr_enable_payload_not_empty_qs)
+    .qs     (intr_enable_upload_payload_not_empty_qs)
   );
 
   //   F[readbuf_watermark]: 8:8
@@ -2061,115 +2061,115 @@
 
 
   // R[intr_test]: V(True)
-  //   F[rx_full]: 0:0
+  //   F[generic_rx_full]: 0:0
   prim_subreg_ext #(
     .DW    (1)
-  ) u_intr_test_rx_full (
+  ) u_intr_test_generic_rx_full (
     .re     (1'b0),
     .we     (intr_test_we),
-    .wd     (intr_test_rx_full_wd),
+    .wd     (intr_test_generic_rx_full_wd),
     .d      ('0),
     .qre    (),
-    .qe     (reg2hw.intr_test.rx_full.qe),
-    .q      (reg2hw.intr_test.rx_full.q),
+    .qe     (reg2hw.intr_test.generic_rx_full.qe),
+    .q      (reg2hw.intr_test.generic_rx_full.q),
     .qs     ()
   );
 
-  //   F[rx_watermark]: 1:1
+  //   F[generic_rx_watermark]: 1:1
   prim_subreg_ext #(
     .DW    (1)
-  ) u_intr_test_rx_watermark (
+  ) u_intr_test_generic_rx_watermark (
     .re     (1'b0),
     .we     (intr_test_we),
-    .wd     (intr_test_rx_watermark_wd),
+    .wd     (intr_test_generic_rx_watermark_wd),
     .d      ('0),
     .qre    (),
-    .qe     (reg2hw.intr_test.rx_watermark.qe),
-    .q      (reg2hw.intr_test.rx_watermark.q),
+    .qe     (reg2hw.intr_test.generic_rx_watermark.qe),
+    .q      (reg2hw.intr_test.generic_rx_watermark.q),
     .qs     ()
   );
 
-  //   F[tx_watermark]: 2:2
+  //   F[generic_tx_watermark]: 2:2
   prim_subreg_ext #(
     .DW    (1)
-  ) u_intr_test_tx_watermark (
+  ) u_intr_test_generic_tx_watermark (
     .re     (1'b0),
     .we     (intr_test_we),
-    .wd     (intr_test_tx_watermark_wd),
+    .wd     (intr_test_generic_tx_watermark_wd),
     .d      ('0),
     .qre    (),
-    .qe     (reg2hw.intr_test.tx_watermark.qe),
-    .q      (reg2hw.intr_test.tx_watermark.q),
+    .qe     (reg2hw.intr_test.generic_tx_watermark.qe),
+    .q      (reg2hw.intr_test.generic_tx_watermark.q),
     .qs     ()
   );
 
-  //   F[rx_error]: 3:3
+  //   F[generic_rx_error]: 3:3
   prim_subreg_ext #(
     .DW    (1)
-  ) u_intr_test_rx_error (
+  ) u_intr_test_generic_rx_error (
     .re     (1'b0),
     .we     (intr_test_we),
-    .wd     (intr_test_rx_error_wd),
+    .wd     (intr_test_generic_rx_error_wd),
     .d      ('0),
     .qre    (),
-    .qe     (reg2hw.intr_test.rx_error.qe),
-    .q      (reg2hw.intr_test.rx_error.q),
+    .qe     (reg2hw.intr_test.generic_rx_error.qe),
+    .q      (reg2hw.intr_test.generic_rx_error.q),
     .qs     ()
   );
 
-  //   F[rx_overflow]: 4:4
+  //   F[generic_rx_overflow]: 4:4
   prim_subreg_ext #(
     .DW    (1)
-  ) u_intr_test_rx_overflow (
+  ) u_intr_test_generic_rx_overflow (
     .re     (1'b0),
     .we     (intr_test_we),
-    .wd     (intr_test_rx_overflow_wd),
+    .wd     (intr_test_generic_rx_overflow_wd),
     .d      ('0),
     .qre    (),
-    .qe     (reg2hw.intr_test.rx_overflow.qe),
-    .q      (reg2hw.intr_test.rx_overflow.q),
+    .qe     (reg2hw.intr_test.generic_rx_overflow.qe),
+    .q      (reg2hw.intr_test.generic_rx_overflow.q),
     .qs     ()
   );
 
-  //   F[tx_underflow]: 5:5
+  //   F[generic_tx_underflow]: 5:5
   prim_subreg_ext #(
     .DW    (1)
-  ) u_intr_test_tx_underflow (
+  ) u_intr_test_generic_tx_underflow (
     .re     (1'b0),
     .we     (intr_test_we),
-    .wd     (intr_test_tx_underflow_wd),
+    .wd     (intr_test_generic_tx_underflow_wd),
     .d      ('0),
     .qre    (),
-    .qe     (reg2hw.intr_test.tx_underflow.qe),
-    .q      (reg2hw.intr_test.tx_underflow.q),
+    .qe     (reg2hw.intr_test.generic_tx_underflow.qe),
+    .q      (reg2hw.intr_test.generic_tx_underflow.q),
     .qs     ()
   );
 
-  //   F[cmdfifo_not_empty]: 6:6
+  //   F[upload_cmdfifo_not_empty]: 6:6
   prim_subreg_ext #(
     .DW    (1)
-  ) u_intr_test_cmdfifo_not_empty (
+  ) u_intr_test_upload_cmdfifo_not_empty (
     .re     (1'b0),
     .we     (intr_test_we),
-    .wd     (intr_test_cmdfifo_not_empty_wd),
+    .wd     (intr_test_upload_cmdfifo_not_empty_wd),
     .d      ('0),
     .qre    (),
-    .qe     (reg2hw.intr_test.cmdfifo_not_empty.qe),
-    .q      (reg2hw.intr_test.cmdfifo_not_empty.q),
+    .qe     (reg2hw.intr_test.upload_cmdfifo_not_empty.qe),
+    .q      (reg2hw.intr_test.upload_cmdfifo_not_empty.q),
     .qs     ()
   );
 
-  //   F[payload_not_empty]: 7:7
+  //   F[upload_payload_not_empty]: 7:7
   prim_subreg_ext #(
     .DW    (1)
-  ) u_intr_test_payload_not_empty (
+  ) u_intr_test_upload_payload_not_empty (
     .re     (1'b0),
     .we     (intr_test_we),
-    .wd     (intr_test_payload_not_empty_wd),
+    .wd     (intr_test_upload_payload_not_empty_wd),
     .d      ('0),
     .qre    (),
-    .qe     (reg2hw.intr_test.payload_not_empty.qe),
-    .q      (reg2hw.intr_test.payload_not_empty.q),
+    .qe     (reg2hw.intr_test.upload_payload_not_empty.qe),
+    .q      (reg2hw.intr_test.upload_payload_not_empty.q),
     .qs     ()
   );
 
@@ -17983,21 +17983,21 @@
   end
   assign intr_state_we = addr_hit[0] & reg_we & !reg_error;
 
-  assign intr_state_rx_full_wd = reg_wdata[0];
+  assign intr_state_generic_rx_full_wd = reg_wdata[0];
 
-  assign intr_state_rx_watermark_wd = reg_wdata[1];
+  assign intr_state_generic_rx_watermark_wd = reg_wdata[1];
 
-  assign intr_state_tx_watermark_wd = reg_wdata[2];
+  assign intr_state_generic_tx_watermark_wd = reg_wdata[2];
 
-  assign intr_state_rx_error_wd = reg_wdata[3];
+  assign intr_state_generic_rx_error_wd = reg_wdata[3];
 
-  assign intr_state_rx_overflow_wd = reg_wdata[4];
+  assign intr_state_generic_rx_overflow_wd = reg_wdata[4];
 
-  assign intr_state_tx_underflow_wd = reg_wdata[5];
+  assign intr_state_generic_tx_underflow_wd = reg_wdata[5];
 
-  assign intr_state_cmdfifo_not_empty_wd = reg_wdata[6];
+  assign intr_state_upload_cmdfifo_not_empty_wd = reg_wdata[6];
 
-  assign intr_state_payload_not_empty_wd = reg_wdata[7];
+  assign intr_state_upload_payload_not_empty_wd = reg_wdata[7];
 
   assign intr_state_readbuf_watermark_wd = reg_wdata[8];
 
@@ -18006,21 +18006,21 @@
   assign intr_state_tpm_header_not_empty_wd = reg_wdata[10];
   assign intr_enable_we = addr_hit[1] & reg_we & !reg_error;
 
-  assign intr_enable_rx_full_wd = reg_wdata[0];
+  assign intr_enable_generic_rx_full_wd = reg_wdata[0];
 
-  assign intr_enable_rx_watermark_wd = reg_wdata[1];
+  assign intr_enable_generic_rx_watermark_wd = reg_wdata[1];
 
-  assign intr_enable_tx_watermark_wd = reg_wdata[2];
+  assign intr_enable_generic_tx_watermark_wd = reg_wdata[2];
 
-  assign intr_enable_rx_error_wd = reg_wdata[3];
+  assign intr_enable_generic_rx_error_wd = reg_wdata[3];
 
-  assign intr_enable_rx_overflow_wd = reg_wdata[4];
+  assign intr_enable_generic_rx_overflow_wd = reg_wdata[4];
 
-  assign intr_enable_tx_underflow_wd = reg_wdata[5];
+  assign intr_enable_generic_tx_underflow_wd = reg_wdata[5];
 
-  assign intr_enable_cmdfifo_not_empty_wd = reg_wdata[6];
+  assign intr_enable_upload_cmdfifo_not_empty_wd = reg_wdata[6];
 
-  assign intr_enable_payload_not_empty_wd = reg_wdata[7];
+  assign intr_enable_upload_payload_not_empty_wd = reg_wdata[7];
 
   assign intr_enable_readbuf_watermark_wd = reg_wdata[8];
 
@@ -18029,21 +18029,21 @@
   assign intr_enable_tpm_header_not_empty_wd = reg_wdata[10];
   assign intr_test_we = addr_hit[2] & reg_we & !reg_error;
 
-  assign intr_test_rx_full_wd = reg_wdata[0];
+  assign intr_test_generic_rx_full_wd = reg_wdata[0];
 
-  assign intr_test_rx_watermark_wd = reg_wdata[1];
+  assign intr_test_generic_rx_watermark_wd = reg_wdata[1];
 
-  assign intr_test_tx_watermark_wd = reg_wdata[2];
+  assign intr_test_generic_tx_watermark_wd = reg_wdata[2];
 
-  assign intr_test_rx_error_wd = reg_wdata[3];
+  assign intr_test_generic_rx_error_wd = reg_wdata[3];
 
-  assign intr_test_rx_overflow_wd = reg_wdata[4];
+  assign intr_test_generic_rx_overflow_wd = reg_wdata[4];
 
-  assign intr_test_tx_underflow_wd = reg_wdata[5];
+  assign intr_test_generic_tx_underflow_wd = reg_wdata[5];
 
-  assign intr_test_cmdfifo_not_empty_wd = reg_wdata[6];
+  assign intr_test_upload_cmdfifo_not_empty_wd = reg_wdata[6];
 
-  assign intr_test_payload_not_empty_wd = reg_wdata[7];
+  assign intr_test_upload_payload_not_empty_wd = reg_wdata[7];
 
   assign intr_test_readbuf_watermark_wd = reg_wdata[8];
 
@@ -19320,28 +19320,28 @@
     reg_rdata_next = '0;
     unique case (1'b1)
       addr_hit[0]: begin
-        reg_rdata_next[0] = intr_state_rx_full_qs;
-        reg_rdata_next[1] = intr_state_rx_watermark_qs;
-        reg_rdata_next[2] = intr_state_tx_watermark_qs;
-        reg_rdata_next[3] = intr_state_rx_error_qs;
-        reg_rdata_next[4] = intr_state_rx_overflow_qs;
-        reg_rdata_next[5] = intr_state_tx_underflow_qs;
-        reg_rdata_next[6] = intr_state_cmdfifo_not_empty_qs;
-        reg_rdata_next[7] = intr_state_payload_not_empty_qs;
+        reg_rdata_next[0] = intr_state_generic_rx_full_qs;
+        reg_rdata_next[1] = intr_state_generic_rx_watermark_qs;
+        reg_rdata_next[2] = intr_state_generic_tx_watermark_qs;
+        reg_rdata_next[3] = intr_state_generic_rx_error_qs;
+        reg_rdata_next[4] = intr_state_generic_rx_overflow_qs;
+        reg_rdata_next[5] = intr_state_generic_tx_underflow_qs;
+        reg_rdata_next[6] = intr_state_upload_cmdfifo_not_empty_qs;
+        reg_rdata_next[7] = intr_state_upload_payload_not_empty_qs;
         reg_rdata_next[8] = intr_state_readbuf_watermark_qs;
         reg_rdata_next[9] = intr_state_readbuf_flip_qs;
         reg_rdata_next[10] = intr_state_tpm_header_not_empty_qs;
       end
 
       addr_hit[1]: begin
-        reg_rdata_next[0] = intr_enable_rx_full_qs;
-        reg_rdata_next[1] = intr_enable_rx_watermark_qs;
-        reg_rdata_next[2] = intr_enable_tx_watermark_qs;
-        reg_rdata_next[3] = intr_enable_rx_error_qs;
-        reg_rdata_next[4] = intr_enable_rx_overflow_qs;
-        reg_rdata_next[5] = intr_enable_tx_underflow_qs;
-        reg_rdata_next[6] = intr_enable_cmdfifo_not_empty_qs;
-        reg_rdata_next[7] = intr_enable_payload_not_empty_qs;
+        reg_rdata_next[0] = intr_enable_generic_rx_full_qs;
+        reg_rdata_next[1] = intr_enable_generic_rx_watermark_qs;
+        reg_rdata_next[2] = intr_enable_generic_tx_watermark_qs;
+        reg_rdata_next[3] = intr_enable_generic_rx_error_qs;
+        reg_rdata_next[4] = intr_enable_generic_rx_overflow_qs;
+        reg_rdata_next[5] = intr_enable_generic_tx_underflow_qs;
+        reg_rdata_next[6] = intr_enable_upload_cmdfifo_not_empty_qs;
+        reg_rdata_next[7] = intr_enable_upload_payload_not_empty_qs;
         reg_rdata_next[8] = intr_enable_readbuf_watermark_qs;
         reg_rdata_next[9] = intr_enable_readbuf_flip_qs;
         reg_rdata_next[10] = intr_enable_tpm_header_not_empty_qs;
diff --git a/hw/top_earlgrey/data/autogen/top_earlgrey.gen.hjson b/hw/top_earlgrey/data/autogen/top_earlgrey.gen.hjson
index 75ac7f1..bba6331 100644
--- a/hw/top_earlgrey/data/autogen/top_earlgrey.gen.hjson
+++ b/hw/top_earlgrey/data/autogen/top_earlgrey.gen.hjson
@@ -12457,49 +12457,49 @@
       module_name: gpio
     }
     {
-      name: spi_device_rx_full
+      name: spi_device_generic_rx_full
       width: 1
       type: interrupt
       module_name: spi_device
     }
     {
-      name: spi_device_rx_watermark
+      name: spi_device_generic_rx_watermark
       width: 1
       type: interrupt
       module_name: spi_device
     }
     {
-      name: spi_device_tx_watermark
+      name: spi_device_generic_tx_watermark
       width: 1
       type: interrupt
       module_name: spi_device
     }
     {
-      name: spi_device_rx_error
+      name: spi_device_generic_rx_error
       width: 1
       type: interrupt
       module_name: spi_device
     }
     {
-      name: spi_device_rx_overflow
+      name: spi_device_generic_rx_overflow
       width: 1
       type: interrupt
       module_name: spi_device
     }
     {
-      name: spi_device_tx_underflow
+      name: spi_device_generic_tx_underflow
       width: 1
       type: interrupt
       module_name: spi_device
     }
     {
-      name: spi_device_cmdfifo_not_empty
+      name: spi_device_upload_cmdfifo_not_empty
       width: 1
       type: interrupt
       module_name: spi_device
     }
     {
-      name: spi_device_payload_not_empty
+      name: spi_device_upload_payload_not_empty
       width: 1
       type: interrupt
       module_name: spi_device
diff --git a/hw/top_earlgrey/rtl/autogen/top_earlgrey.sv b/hw/top_earlgrey/rtl/autogen/top_earlgrey.sv
index f46be4c..2dc76d6 100644
--- a/hw/top_earlgrey/rtl/autogen/top_earlgrey.sv
+++ b/hw/top_earlgrey/rtl/autogen/top_earlgrey.sv
@@ -394,14 +394,14 @@
   logic intr_uart3_rx_timeout;
   logic intr_uart3_rx_parity_err;
   logic [31:0] intr_gpio_gpio;
-  logic intr_spi_device_rx_full;
-  logic intr_spi_device_rx_watermark;
-  logic intr_spi_device_tx_watermark;
-  logic intr_spi_device_rx_error;
-  logic intr_spi_device_rx_overflow;
-  logic intr_spi_device_tx_underflow;
-  logic intr_spi_device_cmdfifo_not_empty;
-  logic intr_spi_device_payload_not_empty;
+  logic intr_spi_device_generic_rx_full;
+  logic intr_spi_device_generic_rx_watermark;
+  logic intr_spi_device_generic_tx_watermark;
+  logic intr_spi_device_generic_rx_error;
+  logic intr_spi_device_generic_rx_overflow;
+  logic intr_spi_device_generic_tx_underflow;
+  logic intr_spi_device_upload_cmdfifo_not_empty;
+  logic intr_spi_device_upload_payload_not_empty;
   logic intr_spi_device_readbuf_watermark;
   logic intr_spi_device_readbuf_flip;
   logic intr_spi_device_tpm_header_not_empty;
@@ -1147,17 +1147,17 @@
       .cio_sd_en_o      (cio_spi_device_sd_en_d2p),
 
       // Interrupt
-      .intr_rx_full_o              (intr_spi_device_rx_full),
-      .intr_rx_watermark_o         (intr_spi_device_rx_watermark),
-      .intr_tx_watermark_o         (intr_spi_device_tx_watermark),
-      .intr_rx_error_o             (intr_spi_device_rx_error),
-      .intr_rx_overflow_o          (intr_spi_device_rx_overflow),
-      .intr_tx_underflow_o         (intr_spi_device_tx_underflow),
-      .intr_cmdfifo_not_empty_o    (intr_spi_device_cmdfifo_not_empty),
-      .intr_payload_not_empty_o    (intr_spi_device_payload_not_empty),
-      .intr_readbuf_watermark_o    (intr_spi_device_readbuf_watermark),
-      .intr_readbuf_flip_o         (intr_spi_device_readbuf_flip),
-      .intr_tpm_header_not_empty_o (intr_spi_device_tpm_header_not_empty),
+      .intr_generic_rx_full_o          (intr_spi_device_generic_rx_full),
+      .intr_generic_rx_watermark_o     (intr_spi_device_generic_rx_watermark),
+      .intr_generic_tx_watermark_o     (intr_spi_device_generic_tx_watermark),
+      .intr_generic_rx_error_o         (intr_spi_device_generic_rx_error),
+      .intr_generic_rx_overflow_o      (intr_spi_device_generic_rx_overflow),
+      .intr_generic_tx_underflow_o     (intr_spi_device_generic_tx_underflow),
+      .intr_upload_cmdfifo_not_empty_o (intr_spi_device_upload_cmdfifo_not_empty),
+      .intr_upload_payload_not_empty_o (intr_spi_device_upload_payload_not_empty),
+      .intr_readbuf_watermark_o        (intr_spi_device_readbuf_watermark),
+      .intr_readbuf_flip_o             (intr_spi_device_readbuf_flip),
+      .intr_tpm_header_not_empty_o     (intr_spi_device_tpm_header_not_empty),
       // [5]: fatal_fault
       .alert_tx_o  ( alert_tx[5:5] ),
       .alert_rx_i  ( alert_rx[5:5] ),
@@ -2639,14 +2639,14 @@
       intr_spi_device_tpm_header_not_empty, // IDs [75 +: 1]
       intr_spi_device_readbuf_flip, // IDs [74 +: 1]
       intr_spi_device_readbuf_watermark, // IDs [73 +: 1]
-      intr_spi_device_payload_not_empty, // IDs [72 +: 1]
-      intr_spi_device_cmdfifo_not_empty, // IDs [71 +: 1]
-      intr_spi_device_tx_underflow, // IDs [70 +: 1]
-      intr_spi_device_rx_overflow, // IDs [69 +: 1]
-      intr_spi_device_rx_error, // IDs [68 +: 1]
-      intr_spi_device_tx_watermark, // IDs [67 +: 1]
-      intr_spi_device_rx_watermark, // IDs [66 +: 1]
-      intr_spi_device_rx_full, // IDs [65 +: 1]
+      intr_spi_device_upload_payload_not_empty, // IDs [72 +: 1]
+      intr_spi_device_upload_cmdfifo_not_empty, // IDs [71 +: 1]
+      intr_spi_device_generic_tx_underflow, // IDs [70 +: 1]
+      intr_spi_device_generic_rx_overflow, // IDs [69 +: 1]
+      intr_spi_device_generic_rx_error, // IDs [68 +: 1]
+      intr_spi_device_generic_tx_watermark, // IDs [67 +: 1]
+      intr_spi_device_generic_rx_watermark, // IDs [66 +: 1]
+      intr_spi_device_generic_rx_full, // IDs [65 +: 1]
       intr_gpio_gpio, // IDs [33 +: 32]
       intr_uart3_rx_parity_err, // IDs [32 +: 1]
       intr_uart3_rx_timeout, // IDs [31 +: 1]
diff --git a/hw/top_earlgrey/sw/autogen/top_earlgrey.c b/hw/top_earlgrey/sw/autogen/top_earlgrey.c
index a904eda..c97f436 100644
--- a/hw/top_earlgrey/sw/autogen/top_earlgrey.c
+++ b/hw/top_earlgrey/sw/autogen/top_earlgrey.c
@@ -77,14 +77,14 @@
   [kTopEarlgreyPlicIrqIdGpioGpio29] = kTopEarlgreyPlicPeripheralGpio,
   [kTopEarlgreyPlicIrqIdGpioGpio30] = kTopEarlgreyPlicPeripheralGpio,
   [kTopEarlgreyPlicIrqIdGpioGpio31] = kTopEarlgreyPlicPeripheralGpio,
-  [kTopEarlgreyPlicIrqIdSpiDeviceRxFull] = kTopEarlgreyPlicPeripheralSpiDevice,
-  [kTopEarlgreyPlicIrqIdSpiDeviceRxWatermark] = kTopEarlgreyPlicPeripheralSpiDevice,
-  [kTopEarlgreyPlicIrqIdSpiDeviceTxWatermark] = kTopEarlgreyPlicPeripheralSpiDevice,
-  [kTopEarlgreyPlicIrqIdSpiDeviceRxError] = kTopEarlgreyPlicPeripheralSpiDevice,
-  [kTopEarlgreyPlicIrqIdSpiDeviceRxOverflow] = kTopEarlgreyPlicPeripheralSpiDevice,
-  [kTopEarlgreyPlicIrqIdSpiDeviceTxUnderflow] = kTopEarlgreyPlicPeripheralSpiDevice,
-  [kTopEarlgreyPlicIrqIdSpiDeviceCmdfifoNotEmpty] = kTopEarlgreyPlicPeripheralSpiDevice,
-  [kTopEarlgreyPlicIrqIdSpiDevicePayloadNotEmpty] = kTopEarlgreyPlicPeripheralSpiDevice,
+  [kTopEarlgreyPlicIrqIdSpiDeviceGenericRxFull] = kTopEarlgreyPlicPeripheralSpiDevice,
+  [kTopEarlgreyPlicIrqIdSpiDeviceGenericRxWatermark] = kTopEarlgreyPlicPeripheralSpiDevice,
+  [kTopEarlgreyPlicIrqIdSpiDeviceGenericTxWatermark] = kTopEarlgreyPlicPeripheralSpiDevice,
+  [kTopEarlgreyPlicIrqIdSpiDeviceGenericRxError] = kTopEarlgreyPlicPeripheralSpiDevice,
+  [kTopEarlgreyPlicIrqIdSpiDeviceGenericRxOverflow] = kTopEarlgreyPlicPeripheralSpiDevice,
+  [kTopEarlgreyPlicIrqIdSpiDeviceGenericTxUnderflow] = kTopEarlgreyPlicPeripheralSpiDevice,
+  [kTopEarlgreyPlicIrqIdSpiDeviceUploadCmdfifoNotEmpty] = kTopEarlgreyPlicPeripheralSpiDevice,
+  [kTopEarlgreyPlicIrqIdSpiDeviceUploadPayloadNotEmpty] = kTopEarlgreyPlicPeripheralSpiDevice,
   [kTopEarlgreyPlicIrqIdSpiDeviceReadbufWatermark] = kTopEarlgreyPlicPeripheralSpiDevice,
   [kTopEarlgreyPlicIrqIdSpiDeviceReadbufFlip] = kTopEarlgreyPlicPeripheralSpiDevice,
   [kTopEarlgreyPlicIrqIdSpiDeviceTpmHeaderNotEmpty] = kTopEarlgreyPlicPeripheralSpiDevice,
diff --git a/hw/top_earlgrey/sw/autogen/top_earlgrey.h b/hw/top_earlgrey/sw/autogen/top_earlgrey.h
index a64d379..bd825c2 100644
--- a/hw/top_earlgrey/sw/autogen/top_earlgrey.h
+++ b/hw/top_earlgrey/sw/autogen/top_earlgrey.h
@@ -1079,14 +1079,14 @@
   kTopEarlgreyPlicIrqIdGpioGpio29 = 62, /**< gpio_gpio 29 */
   kTopEarlgreyPlicIrqIdGpioGpio30 = 63, /**< gpio_gpio 30 */
   kTopEarlgreyPlicIrqIdGpioGpio31 = 64, /**< gpio_gpio 31 */
-  kTopEarlgreyPlicIrqIdSpiDeviceRxFull = 65, /**< spi_device_rx_full */
-  kTopEarlgreyPlicIrqIdSpiDeviceRxWatermark = 66, /**< spi_device_rx_watermark */
-  kTopEarlgreyPlicIrqIdSpiDeviceTxWatermark = 67, /**< spi_device_tx_watermark */
-  kTopEarlgreyPlicIrqIdSpiDeviceRxError = 68, /**< spi_device_rx_error */
-  kTopEarlgreyPlicIrqIdSpiDeviceRxOverflow = 69, /**< spi_device_rx_overflow */
-  kTopEarlgreyPlicIrqIdSpiDeviceTxUnderflow = 70, /**< spi_device_tx_underflow */
-  kTopEarlgreyPlicIrqIdSpiDeviceCmdfifoNotEmpty = 71, /**< spi_device_cmdfifo_not_empty */
-  kTopEarlgreyPlicIrqIdSpiDevicePayloadNotEmpty = 72, /**< spi_device_payload_not_empty */
+  kTopEarlgreyPlicIrqIdSpiDeviceGenericRxFull = 65, /**< spi_device_generic_rx_full */
+  kTopEarlgreyPlicIrqIdSpiDeviceGenericRxWatermark = 66, /**< spi_device_generic_rx_watermark */
+  kTopEarlgreyPlicIrqIdSpiDeviceGenericTxWatermark = 67, /**< spi_device_generic_tx_watermark */
+  kTopEarlgreyPlicIrqIdSpiDeviceGenericRxError = 68, /**< spi_device_generic_rx_error */
+  kTopEarlgreyPlicIrqIdSpiDeviceGenericRxOverflow = 69, /**< spi_device_generic_rx_overflow */
+  kTopEarlgreyPlicIrqIdSpiDeviceGenericTxUnderflow = 70, /**< spi_device_generic_tx_underflow */
+  kTopEarlgreyPlicIrqIdSpiDeviceUploadCmdfifoNotEmpty = 71, /**< spi_device_upload_cmdfifo_not_empty */
+  kTopEarlgreyPlicIrqIdSpiDeviceUploadPayloadNotEmpty = 72, /**< spi_device_upload_payload_not_empty */
   kTopEarlgreyPlicIrqIdSpiDeviceReadbufWatermark = 73, /**< spi_device_readbuf_watermark */
   kTopEarlgreyPlicIrqIdSpiDeviceReadbufFlip = 74, /**< spi_device_readbuf_flip */
   kTopEarlgreyPlicIrqIdSpiDeviceTpmHeaderNotEmpty = 75, /**< spi_device_tpm_header_not_empty */
diff --git a/sw/device/lib/dif/autogen/dif_spi_device_autogen.c b/sw/device/lib/dif/autogen/dif_spi_device_autogen.c
index 77cb50d..ba39ae8 100644
--- a/sw/device/lib/dif/autogen/dif_spi_device_autogen.c
+++ b/sw/device/lib/dif/autogen/dif_spi_device_autogen.c
@@ -53,29 +53,29 @@
 static bool spi_device_get_irq_bit_index(dif_spi_device_irq_t irq,
                                          bitfield_bit32_index_t *index_out) {
   switch (irq) {
-    case kDifSpiDeviceIrqRxFull:
-      *index_out = SPI_DEVICE_INTR_COMMON_RX_FULL_BIT;
+    case kDifSpiDeviceIrqGenericRxFull:
+      *index_out = SPI_DEVICE_INTR_COMMON_GENERIC_RX_FULL_BIT;
       break;
-    case kDifSpiDeviceIrqRxWatermark:
-      *index_out = SPI_DEVICE_INTR_COMMON_RX_WATERMARK_BIT;
+    case kDifSpiDeviceIrqGenericRxWatermark:
+      *index_out = SPI_DEVICE_INTR_COMMON_GENERIC_RX_WATERMARK_BIT;
       break;
-    case kDifSpiDeviceIrqTxWatermark:
-      *index_out = SPI_DEVICE_INTR_COMMON_TX_WATERMARK_BIT;
+    case kDifSpiDeviceIrqGenericTxWatermark:
+      *index_out = SPI_DEVICE_INTR_COMMON_GENERIC_TX_WATERMARK_BIT;
       break;
-    case kDifSpiDeviceIrqRxError:
-      *index_out = SPI_DEVICE_INTR_COMMON_RX_ERROR_BIT;
+    case kDifSpiDeviceIrqGenericRxError:
+      *index_out = SPI_DEVICE_INTR_COMMON_GENERIC_RX_ERROR_BIT;
       break;
-    case kDifSpiDeviceIrqRxOverflow:
-      *index_out = SPI_DEVICE_INTR_COMMON_RX_OVERFLOW_BIT;
+    case kDifSpiDeviceIrqGenericRxOverflow:
+      *index_out = SPI_DEVICE_INTR_COMMON_GENERIC_RX_OVERFLOW_BIT;
       break;
-    case kDifSpiDeviceIrqTxUnderflow:
-      *index_out = SPI_DEVICE_INTR_COMMON_TX_UNDERFLOW_BIT;
+    case kDifSpiDeviceIrqGenericTxUnderflow:
+      *index_out = SPI_DEVICE_INTR_COMMON_GENERIC_TX_UNDERFLOW_BIT;
       break;
-    case kDifSpiDeviceIrqCmdfifoNotEmpty:
-      *index_out = SPI_DEVICE_INTR_COMMON_CMDFIFO_NOT_EMPTY_BIT;
+    case kDifSpiDeviceIrqUploadCmdfifoNotEmpty:
+      *index_out = SPI_DEVICE_INTR_COMMON_UPLOAD_CMDFIFO_NOT_EMPTY_BIT;
       break;
-    case kDifSpiDeviceIrqPayloadNotEmpty:
-      *index_out = SPI_DEVICE_INTR_COMMON_PAYLOAD_NOT_EMPTY_BIT;
+    case kDifSpiDeviceIrqUploadPayloadNotEmpty:
+      *index_out = SPI_DEVICE_INTR_COMMON_UPLOAD_PAYLOAD_NOT_EMPTY_BIT;
       break;
     case kDifSpiDeviceIrqReadbufWatermark:
       *index_out = SPI_DEVICE_INTR_COMMON_READBUF_WATERMARK_BIT;
diff --git a/sw/device/lib/dif/autogen/dif_spi_device_autogen.h b/sw/device/lib/dif/autogen/dif_spi_device_autogen.h
index c3471e5..0402027 100644
--- a/sw/device/lib/dif/autogen/dif_spi_device_autogen.h
+++ b/sw/device/lib/dif/autogen/dif_spi_device_autogen.h
@@ -80,36 +80,36 @@
   /**
    * RX SRAM FIFO Full
    */
-  kDifSpiDeviceIrqRxFull = 0,
+  kDifSpiDeviceIrqGenericRxFull = 0,
   /**
    * RX SRAM FIFO is above the level
    */
-  kDifSpiDeviceIrqRxWatermark = 1,
+  kDifSpiDeviceIrqGenericRxWatermark = 1,
   /**
    * TX SRAM FIFO is under the level
    */
-  kDifSpiDeviceIrqTxWatermark = 2,
+  kDifSpiDeviceIrqGenericTxWatermark = 2,
   /**
    * SDI in FwMode has error
    */
-  kDifSpiDeviceIrqRxError = 3,
+  kDifSpiDeviceIrqGenericRxError = 3,
   /**
    * RX Async FIFO overflow
    */
-  kDifSpiDeviceIrqRxOverflow = 4,
+  kDifSpiDeviceIrqGenericRxOverflow = 4,
   /**
    * TX Async FIFO underflow
    */
-  kDifSpiDeviceIrqTxUnderflow = 5,
+  kDifSpiDeviceIrqGenericTxUnderflow = 5,
   /**
    * Upload Command FIFO is not empty
    */
-  kDifSpiDeviceIrqCmdfifoNotEmpty = 6,
+  kDifSpiDeviceIrqUploadCmdfifoNotEmpty = 6,
   /**
    * Upload paylod is not empty.  The event occurs after SPI transaction
    * completed
    */
-  kDifSpiDeviceIrqPayloadNotEmpty = 7,
+  kDifSpiDeviceIrqUploadPayloadNotEmpty = 7,
   /**
    * Read Buffer Threshold event.  The host system accesses greater than or
    * equal to the threshold of a buffer.
diff --git a/sw/device/lib/dif/autogen/dif_spi_device_autogen_unittest.cc b/sw/device/lib/dif/autogen/dif_spi_device_autogen_unittest.cc
index 2ac184e..d99066d 100644
--- a/sw/device/lib/dif/autogen/dif_spi_device_autogen_unittest.cc
+++ b/sw/device/lib/dif/autogen/dif_spi_device_autogen_unittest.cc
@@ -91,17 +91,17 @@
 TEST_F(IrqIsPendingTest, NullArgs) {
   bool is_pending;
 
-  EXPECT_EQ(dif_spi_device_irq_is_pending(nullptr, kDifSpiDeviceIrqRxFull,
-                                          &is_pending),
+  EXPECT_EQ(dif_spi_device_irq_is_pending(
+                nullptr, kDifSpiDeviceIrqGenericRxFull, &is_pending),
             kDifBadArg);
 
-  EXPECT_EQ(dif_spi_device_irq_is_pending(&spi_device_, kDifSpiDeviceIrqRxFull,
-                                          nullptr),
+  EXPECT_EQ(dif_spi_device_irq_is_pending(
+                &spi_device_, kDifSpiDeviceIrqGenericRxFull, nullptr),
             kDifBadArg);
 
-  EXPECT_EQ(
-      dif_spi_device_irq_is_pending(nullptr, kDifSpiDeviceIrqRxFull, nullptr),
-      kDifBadArg);
+  EXPECT_EQ(dif_spi_device_irq_is_pending(
+                nullptr, kDifSpiDeviceIrqGenericRxFull, nullptr),
+            kDifBadArg);
 }
 
 TEST_F(IrqIsPendingTest, BadIrq) {
@@ -119,9 +119,9 @@
   // Get the first IRQ state.
   irq_state = false;
   EXPECT_READ32(SPI_DEVICE_INTR_STATE_REG_OFFSET,
-                {{SPI_DEVICE_INTR_STATE_RX_FULL_BIT, true}});
-  EXPECT_EQ(dif_spi_device_irq_is_pending(&spi_device_, kDifSpiDeviceIrqRxFull,
-                                          &irq_state),
+                {{SPI_DEVICE_INTR_STATE_GENERIC_RX_FULL_BIT, true}});
+  EXPECT_EQ(dif_spi_device_irq_is_pending(
+                &spi_device_, kDifSpiDeviceIrqGenericRxFull, &irq_state),
             kDifOk);
   EXPECT_TRUE(irq_state);
 
@@ -151,8 +151,9 @@
 class IrqAcknowledgeTest : public SpiDeviceTest {};
 
 TEST_F(IrqAcknowledgeTest, NullArgs) {
-  EXPECT_EQ(dif_spi_device_irq_acknowledge(nullptr, kDifSpiDeviceIrqRxFull),
-            kDifBadArg);
+  EXPECT_EQ(
+      dif_spi_device_irq_acknowledge(nullptr, kDifSpiDeviceIrqGenericRxFull),
+      kDifBadArg);
 }
 
 TEST_F(IrqAcknowledgeTest, BadIrq) {
@@ -164,10 +165,10 @@
 TEST_F(IrqAcknowledgeTest, Success) {
   // Clear the first IRQ state.
   EXPECT_WRITE32(SPI_DEVICE_INTR_STATE_REG_OFFSET,
-                 {{SPI_DEVICE_INTR_STATE_RX_FULL_BIT, true}});
-  EXPECT_EQ(
-      dif_spi_device_irq_acknowledge(&spi_device_, kDifSpiDeviceIrqRxFull),
-      kDifOk);
+                 {{SPI_DEVICE_INTR_STATE_GENERIC_RX_FULL_BIT, true}});
+  EXPECT_EQ(dif_spi_device_irq_acknowledge(&spi_device_,
+                                           kDifSpiDeviceIrqGenericRxFull),
+            kDifOk);
 
   // Clear the last IRQ state.
   EXPECT_WRITE32(SPI_DEVICE_INTR_STATE_REG_OFFSET,
@@ -180,7 +181,7 @@
 class IrqForceTest : public SpiDeviceTest {};
 
 TEST_F(IrqForceTest, NullArgs) {
-  EXPECT_EQ(dif_spi_device_irq_force(nullptr, kDifSpiDeviceIrqRxFull),
+  EXPECT_EQ(dif_spi_device_irq_force(nullptr, kDifSpiDeviceIrqGenericRxFull),
             kDifBadArg);
 }
 
@@ -193,9 +194,10 @@
 TEST_F(IrqForceTest, Success) {
   // Force first IRQ.
   EXPECT_WRITE32(SPI_DEVICE_INTR_TEST_REG_OFFSET,
-                 {{SPI_DEVICE_INTR_TEST_RX_FULL_BIT, true}});
-  EXPECT_EQ(dif_spi_device_irq_force(&spi_device_, kDifSpiDeviceIrqRxFull),
-            kDifOk);
+                 {{SPI_DEVICE_INTR_TEST_GENERIC_RX_FULL_BIT, true}});
+  EXPECT_EQ(
+      dif_spi_device_irq_force(&spi_device_, kDifSpiDeviceIrqGenericRxFull),
+      kDifOk);
 
   // Force last IRQ.
   EXPECT_WRITE32(SPI_DEVICE_INTR_TEST_REG_OFFSET,
@@ -210,17 +212,17 @@
 TEST_F(IrqGetEnabledTest, NullArgs) {
   dif_toggle_t irq_state;
 
-  EXPECT_EQ(dif_spi_device_irq_get_enabled(nullptr, kDifSpiDeviceIrqRxFull,
-                                           &irq_state),
+  EXPECT_EQ(dif_spi_device_irq_get_enabled(
+                nullptr, kDifSpiDeviceIrqGenericRxFull, &irq_state),
             kDifBadArg);
 
-  EXPECT_EQ(dif_spi_device_irq_get_enabled(&spi_device_, kDifSpiDeviceIrqRxFull,
-                                           nullptr),
+  EXPECT_EQ(dif_spi_device_irq_get_enabled(
+                &spi_device_, kDifSpiDeviceIrqGenericRxFull, nullptr),
             kDifBadArg);
 
-  EXPECT_EQ(
-      dif_spi_device_irq_get_enabled(nullptr, kDifSpiDeviceIrqRxFull, nullptr),
-      kDifBadArg);
+  EXPECT_EQ(dif_spi_device_irq_get_enabled(
+                nullptr, kDifSpiDeviceIrqGenericRxFull, nullptr),
+            kDifBadArg);
 }
 
 TEST_F(IrqGetEnabledTest, BadIrq) {
@@ -238,9 +240,9 @@
   // First IRQ is enabled.
   irq_state = kDifToggleDisabled;
   EXPECT_READ32(SPI_DEVICE_INTR_ENABLE_REG_OFFSET,
-                {{SPI_DEVICE_INTR_ENABLE_RX_FULL_BIT, true}});
-  EXPECT_EQ(dif_spi_device_irq_get_enabled(&spi_device_, kDifSpiDeviceIrqRxFull,
-                                           &irq_state),
+                {{SPI_DEVICE_INTR_ENABLE_GENERIC_RX_FULL_BIT, true}});
+  EXPECT_EQ(dif_spi_device_irq_get_enabled(
+                &spi_device_, kDifSpiDeviceIrqGenericRxFull, &irq_state),
             kDifOk);
   EXPECT_EQ(irq_state, kDifToggleEnabled);
 
@@ -259,8 +261,8 @@
 TEST_F(IrqSetEnabledTest, NullArgs) {
   dif_toggle_t irq_state = kDifToggleEnabled;
 
-  EXPECT_EQ(dif_spi_device_irq_set_enabled(nullptr, kDifSpiDeviceIrqRxFull,
-                                           irq_state),
+  EXPECT_EQ(dif_spi_device_irq_set_enabled(
+                nullptr, kDifSpiDeviceIrqGenericRxFull, irq_state),
             kDifBadArg);
 }
 
@@ -278,9 +280,9 @@
   // Enable first IRQ.
   irq_state = kDifToggleEnabled;
   EXPECT_MASK32(SPI_DEVICE_INTR_ENABLE_REG_OFFSET,
-                {{SPI_DEVICE_INTR_ENABLE_RX_FULL_BIT, 0x1, true}});
-  EXPECT_EQ(dif_spi_device_irq_set_enabled(&spi_device_, kDifSpiDeviceIrqRxFull,
-                                           irq_state),
+                {{SPI_DEVICE_INTR_ENABLE_GENERIC_RX_FULL_BIT, 0x1, true}});
+  EXPECT_EQ(dif_spi_device_irq_set_enabled(
+                &spi_device_, kDifSpiDeviceIrqGenericRxFull, irq_state),
             kDifOk);
 
   // Disable last IRQ.
diff --git a/sw/device/tests/autogen/plic_all_irqs_test.c b/sw/device/tests/autogen/plic_all_irqs_test.c
index 31c0561..68498bb 100644
--- a/sw/device/tests/autogen/plic_all_irqs_test.c
+++ b/sw/device/tests/autogen/plic_all_irqs_test.c
@@ -562,7 +562,7 @@
     case kTopEarlgreyPlicPeripheralSpiDevice: {
       dif_spi_device_irq_t irq = (dif_spi_device_irq_t)(
           plic_irq_id -
-          (dif_rv_plic_irq_id_t)kTopEarlgreyPlicIrqIdSpiDeviceRxFull);
+          (dif_rv_plic_irq_id_t)kTopEarlgreyPlicIrqIdSpiDeviceGenericRxFull);
       CHECK(irq == spi_device_irq_expected,
             "Incorrect spi_device IRQ triggered: exp = %d, obs = %d",
             spi_device_irq_expected, irq);
@@ -1256,7 +1256,7 @@
   }
 
   peripheral_expected = kTopEarlgreyPlicPeripheralSpiDevice;
-  for (dif_spi_device_irq_t irq = kDifSpiDeviceIrqRxFull;
+  for (dif_spi_device_irq_t irq = kDifSpiDeviceIrqGenericRxFull;
        irq <= kDifSpiDeviceIrqTpmHeaderNotEmpty; ++irq) {
     spi_device_irq_expected = irq;
     LOG_INFO("Triggering spi_device IRQ %d.", irq);
diff --git a/sw/device/tests/sim_dv/spi_tx_rx_test.c b/sw/device/tests/sim_dv/spi_tx_rx_test.c
index e9bbec6..6bcebe8 100644
--- a/sw/device/tests/sim_dv/spi_tx_rx_test.c
+++ b/sw/device/tests/sim_dv/spi_tx_rx_test.c
@@ -82,30 +82,30 @@
   // Correlate the interrupt fired at PLIC with SPI DEVICE.
   dif_spi_device_irq_t spi_device_irq = 0;
   switch (plic_irq_id) {
-    case kTopEarlgreyPlicIrqIdSpiDeviceRxFull:
-      spi_device_irq = kDifSpiDeviceIrqRxFull;
+    case kTopEarlgreyPlicIrqIdSpiDeviceGenericRxFull:
+      spi_device_irq = kDifSpiDeviceIrqGenericRxFull;
       CHECK(expected_irqs[spi_device_irq], "Unexpected RX full interrupt");
       break;
-    case kTopEarlgreyPlicIrqIdSpiDeviceRxWatermark:
-      spi_device_irq = kDifSpiDeviceIrqRxWatermark;
+    case kTopEarlgreyPlicIrqIdSpiDeviceGenericRxWatermark:
+      spi_device_irq = kDifSpiDeviceIrqGenericRxWatermark;
       CHECK(expected_irqs[spi_device_irq],
             "Unexpected RX above level interrupt");
       break;
-    case kTopEarlgreyPlicIrqIdSpiDeviceTxWatermark:
-      spi_device_irq = kDifSpiDeviceIrqTxWatermark;
+    case kTopEarlgreyPlicIrqIdSpiDeviceGenericTxWatermark:
+      spi_device_irq = kDifSpiDeviceIrqGenericTxWatermark;
       CHECK(expected_irqs[spi_device_irq],
             "Unexpected TX below level interrupt");
       break;
-    case kTopEarlgreyPlicIrqIdSpiDeviceRxError:
-      spi_device_irq = kDifSpiDeviceIrqRxError;
+    case kTopEarlgreyPlicIrqIdSpiDeviceGenericRxError:
+      spi_device_irq = kDifSpiDeviceIrqGenericRxError;
       CHECK(expected_irqs[spi_device_irq], "Unexpected RX error interrupt");
       break;
-    case kTopEarlgreyPlicIrqIdSpiDeviceRxOverflow:
-      spi_device_irq = kDifSpiDeviceIrqRxOverflow;
+    case kTopEarlgreyPlicIrqIdSpiDeviceGenericRxOverflow:
+      spi_device_irq = kDifSpiDeviceIrqGenericRxOverflow;
       CHECK(expected_irqs[spi_device_irq], "Unexpected RX overflow interrupt");
       break;
-    case kTopEarlgreyPlicIrqIdSpiDeviceTxUnderflow:
-      spi_device_irq = kDifSpiDeviceIrqTxUnderflow;
+    case kTopEarlgreyPlicIrqIdSpiDeviceGenericTxUnderflow:
+      spi_device_irq = kDifSpiDeviceIrqGenericTxUnderflow;
       CHECK(expected_irqs[spi_device_irq], "Unexpected TX underflow interrupt");
       // TxUnderflow keeps firing as TX fifo is empty but TB controls host to
       // keep sending data and requesting data from device, so disable this
@@ -113,7 +113,7 @@
       // back to the main program, disable the interrupt here instead of in the
       // main program.
       CHECK_DIF_OK(dif_spi_device_irq_set_enabled(
-          &spi_device, kDifSpiDeviceIrqTxUnderflow, kDifToggleDisabled));
+          &spi_device, kDifSpiDeviceIrqGenericTxUnderflow, kDifToggleDisabled));
       break;
     default:
       LOG_ERROR("Unexpected interrupt (at PLIC): %d", plic_irq_id);
@@ -147,17 +147,17 @@
   CHECK_DIF_OK(dif_spi_device_configure(spi_device, spi_device_config));
 
   CHECK_DIF_OK(dif_spi_device_irq_set_enabled(
-      spi_device, kDifSpiDeviceIrqRxFull, kDifToggleEnabled));
+      spi_device, kDifSpiDeviceIrqGenericRxFull, kDifToggleEnabled));
   CHECK_DIF_OK(dif_spi_device_irq_set_enabled(
-      spi_device, kDifSpiDeviceIrqRxWatermark, kDifToggleEnabled));
+      spi_device, kDifSpiDeviceIrqGenericRxWatermark, kDifToggleEnabled));
   CHECK_DIF_OK(dif_spi_device_irq_set_enabled(
-      spi_device, kDifSpiDeviceIrqTxWatermark, kDifToggleEnabled));
+      spi_device, kDifSpiDeviceIrqGenericTxWatermark, kDifToggleEnabled));
   CHECK_DIF_OK(dif_spi_device_irq_set_enabled(
-      spi_device, kDifSpiDeviceIrqRxError, kDifToggleEnabled));
+      spi_device, kDifSpiDeviceIrqGenericRxError, kDifToggleEnabled));
   CHECK_DIF_OK(dif_spi_device_irq_set_enabled(
-      spi_device, kDifSpiDeviceIrqRxOverflow, kDifToggleEnabled));
+      spi_device, kDifSpiDeviceIrqGenericRxOverflow, kDifToggleEnabled));
   CHECK_DIF_OK(dif_spi_device_irq_set_enabled(
-      spi_device, kDifSpiDeviceIrqTxUnderflow, kDifToggleEnabled));
+      spi_device, kDifSpiDeviceIrqGenericTxUnderflow, kDifToggleEnabled));
 
   // Initialize the volatile irq variables.
   for (int i = 0; i < SPI_DEVICE_NUM_IRQS; i++) {
@@ -177,53 +177,59 @@
   // Set the priority of SPI DEVICE interrupts at PLIC to be >=1 (so ensure the
   // target does get interrupted).
   CHECK_DIF_OK(dif_rv_plic_irq_set_priority(
-      plic, kTopEarlgreyPlicIrqIdSpiDeviceRxFull, kDifRvPlicMaxPriority));
+      plic, kTopEarlgreyPlicIrqIdSpiDeviceGenericRxFull,
+      kDifRvPlicMaxPriority));
   CHECK_DIF_OK(dif_rv_plic_irq_set_priority(
-      plic, kTopEarlgreyPlicIrqIdSpiDeviceRxWatermark, kDifRvPlicMaxPriority));
+      plic, kTopEarlgreyPlicIrqIdSpiDeviceGenericRxWatermark,
+      kDifRvPlicMaxPriority));
   CHECK_DIF_OK(dif_rv_plic_irq_set_priority(
-      plic, kTopEarlgreyPlicIrqIdSpiDeviceTxWatermark, kDifRvPlicMaxPriority));
+      plic, kTopEarlgreyPlicIrqIdSpiDeviceGenericTxWatermark,
+      kDifRvPlicMaxPriority));
   CHECK_DIF_OK(dif_rv_plic_irq_set_priority(
-      plic, kTopEarlgreyPlicIrqIdSpiDeviceRxError, kDifRvPlicMaxPriority));
+      plic, kTopEarlgreyPlicIrqIdSpiDeviceGenericRxError,
+      kDifRvPlicMaxPriority));
   CHECK_DIF_OK(dif_rv_plic_irq_set_priority(
-      plic, kTopEarlgreyPlicIrqIdSpiDeviceRxOverflow, kDifRvPlicMaxPriority));
+      plic, kTopEarlgreyPlicIrqIdSpiDeviceGenericRxOverflow,
+      kDifRvPlicMaxPriority));
   CHECK_DIF_OK(dif_rv_plic_irq_set_priority(
-      plic, kTopEarlgreyPlicIrqIdSpiDeviceTxUnderflow, kDifRvPlicMaxPriority));
+      plic, kTopEarlgreyPlicIrqIdSpiDeviceGenericTxUnderflow,
+      kDifRvPlicMaxPriority));
 
   // Set the threshold for the Ibex to 0.
   CHECK_DIF_OK(
       dif_rv_plic_target_set_threshold(plic, kTopEarlgreyPlicTargetIbex0, 0x0));
 
   CHECK_DIF_OK(dif_rv_plic_irq_set_enabled(
-      plic, kTopEarlgreyPlicIrqIdSpiDeviceRxFull, kTopEarlgreyPlicTargetIbex0,
-      kDifToggleEnabled));
-
-  CHECK_DIF_OK(dif_rv_plic_irq_set_enabled(
-      plic, kTopEarlgreyPlicIrqIdSpiDeviceRxWatermark,
+      plic, kTopEarlgreyPlicIrqIdSpiDeviceGenericRxFull,
       kTopEarlgreyPlicTargetIbex0, kDifToggleEnabled));
 
   CHECK_DIF_OK(dif_rv_plic_irq_set_enabled(
-      plic, kTopEarlgreyPlicIrqIdSpiDeviceTxWatermark,
+      plic, kTopEarlgreyPlicIrqIdSpiDeviceGenericRxWatermark,
       kTopEarlgreyPlicTargetIbex0, kDifToggleEnabled));
 
   CHECK_DIF_OK(dif_rv_plic_irq_set_enabled(
-      plic, kTopEarlgreyPlicIrqIdSpiDeviceRxError, kTopEarlgreyPlicTargetIbex0,
-      kDifToggleEnabled));
-
-  CHECK_DIF_OK(dif_rv_plic_irq_set_enabled(
-      plic, kTopEarlgreyPlicIrqIdSpiDeviceRxOverflow,
+      plic, kTopEarlgreyPlicIrqIdSpiDeviceGenericTxWatermark,
       kTopEarlgreyPlicTargetIbex0, kDifToggleEnabled));
 
   CHECK_DIF_OK(dif_rv_plic_irq_set_enabled(
-      plic, kTopEarlgreyPlicIrqIdSpiDeviceTxUnderflow,
+      plic, kTopEarlgreyPlicIrqIdSpiDeviceGenericRxError,
+      kTopEarlgreyPlicTargetIbex0, kDifToggleEnabled));
+
+  CHECK_DIF_OK(dif_rv_plic_irq_set_enabled(
+      plic, kTopEarlgreyPlicIrqIdSpiDeviceGenericRxOverflow,
+      kTopEarlgreyPlicTargetIbex0, kDifToggleEnabled));
+
+  CHECK_DIF_OK(dif_rv_plic_irq_set_enabled(
+      plic, kTopEarlgreyPlicIrqIdSpiDeviceGenericTxUnderflow,
       kTopEarlgreyPlicTargetIbex0, kDifToggleEnabled));
 }
 
 static bool exp_irqs_fired(void) {
-  return fired_irqs[kDifSpiDeviceIrqRxWatermark] &&
-         fired_irqs[kDifSpiDeviceIrqTxWatermark] &&
-         fired_irqs[kDifSpiDeviceIrqRxOverflow] &&
-         fired_irqs[kDifSpiDeviceIrqTxUnderflow] &&
-         fired_irqs[kDifSpiDeviceIrqRxFull];
+  return fired_irqs[kDifSpiDeviceIrqGenericRxWatermark] &&
+         fired_irqs[kDifSpiDeviceIrqGenericTxWatermark] &&
+         fired_irqs[kDifSpiDeviceIrqGenericRxOverflow] &&
+         fired_irqs[kDifSpiDeviceIrqGenericTxUnderflow] &&
+         fired_irqs[kDifSpiDeviceIrqGenericRxFull];
 }
 
 static bool execute_test(const dif_spi_device_t *spi_device,
@@ -244,30 +250,30 @@
 
   CHECK_DIF_OK(dif_spi_device_set_irq_levels(
       spi_device, SPI_DEVICE_DATASET_SIZE, SPI_DEVICE_DATASET_SIZE / 2));
-  expected_irqs[kDifSpiDeviceIrqTxWatermark] = true;
+  expected_irqs[kDifSpiDeviceIrqGenericTxWatermark] = true;
 
   bool read_rx_fifo_done = false;
   while (!read_rx_fifo_done || !exp_irqs_fired()) {
     // set rx tx level back to default value so TxBelowLevel irq won't trigger
-    if (fired_irqs[kDifSpiDeviceIrqTxWatermark] &&
-        expected_irqs[kDifSpiDeviceIrqTxWatermark]) {
+    if (fired_irqs[kDifSpiDeviceIrqGenericTxWatermark] &&
+        expected_irqs[kDifSpiDeviceIrqGenericTxWatermark]) {
       CHECK_DIF_OK(dif_spi_device_set_irq_levels(spi_device,
                                                  SPI_DEVICE_DATASET_SIZE, 0));
-      expected_irqs[kDifSpiDeviceIrqTxWatermark] = false;
-      expected_irqs[kDifSpiDeviceIrqRxWatermark] = true;
+      expected_irqs[kDifSpiDeviceIrqGenericTxWatermark] = false;
+      expected_irqs[kDifSpiDeviceIrqGenericRxWatermark] = true;
       LOG_INFO("SPI_DEVICE tx_below_level interrupt fired.");
     }
 
     // wait for SPI_HOST to send 128 bytes and trigger RxAboveLevel irq
-    if (fired_irqs[kDifSpiDeviceIrqRxWatermark] &&
-        expected_irqs[kDifSpiDeviceIrqRxWatermark]) {
-      expected_irqs[kDifSpiDeviceIrqRxWatermark] = false;
+    if (fired_irqs[kDifSpiDeviceIrqGenericRxWatermark] &&
+        expected_irqs[kDifSpiDeviceIrqGenericRxWatermark]) {
+      expected_irqs[kDifSpiDeviceIrqGenericRxWatermark] = false;
       LOG_INFO("SPI_DEVICE rx_above_level interrupt fired.");
     }
 
     // when 128 bytes received in RX_FIFO from SPI_HOST,
     // read out and compare against the expected data
-    if (fired_irqs[kDifSpiDeviceIrqRxWatermark] && !read_rx_fifo_done) {
+    if (fired_irqs[kDifSpiDeviceIrqGenericRxWatermark] && !read_rx_fifo_done) {
       size_t bytes_recved = 0;
       uint8_t spi_device_rx_data[SPI_DEVICE_DATASET_SIZE];
       CHECK_DIF_OK(dif_spi_device_recv(spi_device, spi_device_config,
@@ -282,8 +288,8 @@
             bytes_recved, SPI_DEVICE_DATASET_SIZE);
       }
       // expect SPI_HOST to send another 1024 bytes to fill RX SRAM FIFO
-      expected_irqs[kDifSpiDeviceIrqTxUnderflow] = true;
-      fired_irqs[kDifSpiDeviceIrqRxWatermark] = false;
+      expected_irqs[kDifSpiDeviceIrqGenericTxUnderflow] = true;
+      fired_irqs[kDifSpiDeviceIrqGenericRxWatermark] = false;
 
       // Check data consistency.
       LOG_INFO("Checking the received SPI_HOST RX_FIFO data for consistency.");
@@ -294,23 +300,23 @@
       }
     }
 
-    if (read_rx_fifo_done && fired_irqs[kDifSpiDeviceIrqTxUnderflow]) {
-      expected_irqs[kDifSpiDeviceIrqRxWatermark] = true;
-      expected_irqs[kDifSpiDeviceIrqTxUnderflow] = false;
+    if (read_rx_fifo_done && fired_irqs[kDifSpiDeviceIrqGenericTxUnderflow]) {
+      expected_irqs[kDifSpiDeviceIrqGenericRxWatermark] = true;
+      expected_irqs[kDifSpiDeviceIrqGenericTxUnderflow] = false;
       LOG_INFO("SPI_DEVICE Tx underflow fired.");
     }
 
-    if (read_rx_fifo_done && fired_irqs[kDifSpiDeviceIrqRxWatermark]) {
-      expected_irqs[kDifSpiDeviceIrqRxWatermark] = false;
-      expected_irqs[kDifSpiDeviceIrqRxFull] = true;
+    if (read_rx_fifo_done && fired_irqs[kDifSpiDeviceIrqGenericRxWatermark]) {
+      expected_irqs[kDifSpiDeviceIrqGenericRxWatermark] = false;
+      expected_irqs[kDifSpiDeviceIrqGenericRxFull] = true;
       LOG_INFO("SPI_DEVICE RX Above level interrupt fired.");
     }
 
     // After RX SRAM FIFO full, expect RX async FIFO overflow irq
-    if (fired_irqs[kDifSpiDeviceIrqRxFull] &&
-        !fired_irqs[kDifSpiDeviceIrqRxOverflow]) {
-      expected_irqs[kDifSpiDeviceIrqRxFull] = false;
-      expected_irqs[kDifSpiDeviceIrqRxOverflow] = true;
+    if (fired_irqs[kDifSpiDeviceIrqGenericRxFull] &&
+        !fired_irqs[kDifSpiDeviceIrqGenericRxOverflow]) {
+      expected_irqs[kDifSpiDeviceIrqGenericRxFull] = false;
+      expected_irqs[kDifSpiDeviceIrqGenericRxOverflow] = true;
       LOG_INFO("SPI_DEVICE RX_FIFO full interrupt fired.");
     }