Port Width Fixes: Required for syn
Synopsys synthesis will not resolve port mismatches in real time and
mismatches therefore result in matcha syn runs failing.
This CL topic fixes port width mismatches in matcha and ips
Change-Id: I70c17726fdc8ba493879af5901e491f38038a7be
diff --git a/axi2sramcrs/rtl/axi2sramcrs.v b/axi2sramcrs/rtl/axi2sramcrs.v
index 216c01a..c6fb755 100644
--- a/axi2sramcrs/rtl/axi2sramcrs.v
+++ b/axi2sramcrs/rtl/axi2sramcrs.v
@@ -148,7 +148,19 @@
wire bready_lite_m;
wire [1:0] bresp_lite_m;
-axi_upsizer u_upsizer(/*AUTOINST*/
+axi_upsizer #(
+ .ARID_WIDTH (ARID_WIDTH),
+ .AWID_WIDTH (AWID_WIDTH),
+ .ADDR_WIDTH (ADDR_WIDTH),
+ .US_DATA_WIDTH (US_DATA_WIDTH),
+ .DS_DATA_WIDTH (DS_DATA_WIDTH),
+ .USER_WIDTH (USER_WIDTH),
+ .IS_AXI3 (IS_AXI3),
+ .RD_ISS (RD_ISS),
+ .WR_ISS (WR_ISS),
+ .DS_WSTRB_WIDTH (DS_WSTRB_WIDTH),
+ .US_WSTRB_WIDTH (US_WSTRB_WIDTH))
+u_upsizer(/*AUTOINST*/
// Outputs
.awid_m (awid_m[AWID_WIDTH-1:0]),
.awaddr_m (awaddr_m[ADDR_WIDTH-1:0]),
@@ -245,7 +257,12 @@
.arqos_s (4'b0));
-axi2axilite u_axi2axilite(/*AUTOINST*/
+axi2axilite #(
+ .ARID_WIDTH (ARID_WIDTH),
+ .AWID_WIDTH (AWID_WIDTH),
+ .ADDR_WIDTH (ADDR_WIDTH),
+ .USER_WIDTH (USER_WIDTH))
+u_axi2axilite(/*AUTOINST*/
// Outputs
.awready_s (awready_m),
.wready_s (wready_m),
@@ -317,7 +334,12 @@
.rdata_m (32'b0),//Tie
.rresp_m (2'b0));//Tie
-axilite2sram u_axilite2sram(/*AUTOINST*/
+axilite2sram #(
+ .ARID_WIDTH (ARID_WIDTH),
+ .AWID_WIDTH (AWID_WIDTH),
+ .ADDR_WIDTH (ADDR_WIDTH),
+ .USER_WIDTH (USER_WIDTH))
+u_axilite2sram(/*AUTOINST*/
// Outputs
.awready_s (awready_lite_m),
.wready_s (wready_lite_m),
