Integrate Yocto ISP codes into opensecura
Change-Id: I3929e6e0504d218b1e5a6dc1a2825aa0151c027d
diff --git a/axi2sramcrs/BUILD b/axi2sramcrs/BUILD
new file mode 100644
index 0000000..0f51650
--- /dev/null
+++ b/axi2sramcrs/BUILD
@@ -0,0 +1,8 @@
+# Copyright 2023 Google LLC
+# Copyright 2023 Vivante Corporation
+# Licensed under the Apache License, Version 2.0, see LICENSE for details.
+# SPDX-License-Identifier: Apache-2.0
+
+package(default_visibility = ["//visibility:public"])
+
+exports_files(["BUILD"])
diff --git a/axi2sramcrs/axi2sramcrs.core b/axi2sramcrs/axi2sramcrs.core
new file mode 100644
index 0000000..edd0b79
--- /dev/null
+++ b/axi2sramcrs/axi2sramcrs.core
@@ -0,0 +1,83 @@
+CAPI=2:
+# Copyright 2023 Google LLC
+# Copyright 2023 Vivante Corporation
+# Copyright lowRISC contributors.
+# Licensed under the Apache License, Version 2.0, see LICENSE for details.
+# SPDX-License-Identifier: Apache-2.0
+name: "vsi:ip:axi2sramcrs:0.1"
+description: "axi2sramcrs"
+filesets:
+ files_rtl:
+ depend:
+ - vsi:axi2sramcrs:includes
+ files:
+ - rtl/axi2sramcrs.v
+ - rtl/axilite2sram.v
+ - rtl/axi2axilite/axi2axilite.v
+ - rtl/upsizer/axi_upsizer.v
+ - rtl/upsizer/upsize_rd_addr_fmt.v
+ - rtl/upsizer/upsize_rd_cam_slice.v
+ - rtl/upsizer/upsize_rd_chan.v
+ - rtl/upsizer/upsize_resp_cam_slice.v
+ - rtl/upsizer/upsize_wr_addr_fmt.v
+ - rtl/upsizer/upsize_wr_cntrl.v
+ - rtl/upsizer/upsize_wr_merge_buffer.v
+ - rtl/upsizer/upsize_wr_resp_block.v
+ - rtl/upsizer/maskcntl.v
+ - rtl/upsizer/upsize_master_domain.v
+ - rtl/upsizer/upsize_slave_domain.v
+ - rtl/share/axi_slice/axi_slice.v
+ - rtl/share/axi_slice/axi_ful_regd_slice.v
+ - rtl/share/axi_slice/axi_fwd_regd_slice.v
+ - rtl/share/axi_slice/axi_rev_regd_slice.v
+ file_type: systemVerilogSource
+
+ files_verilator_waiver:
+ depend:
+ # common waivers
+ - lowrisc:lint:common
+ - lowrisc:lint:comportable
+ files:
+ - lint/axi2sramcrs.vlt
+ file_type: vlt
+
+ files_ascentlint_waiver:
+ depend:
+ # common waivers
+ - lowrisc:lint:common
+ - lowrisc:lint:comportable
+ files:
+ - lint/axi2sramcrs.waiver
+ file_type: waiver
+
+ files_veriblelint_waiver:
+ depend:
+ # common waivers
+ - lowrisc:lint:common
+ - lowrisc:lint:comportable
+
+parameters:
+ SYNTHESIS:
+ datatype: bool
+ paramtype: vlogdefine
+
+
+targets:
+ default: &default_target
+ filesets:
+ - tool_verilator ? (files_verilator_waiver)
+ - tool_ascentlint ? (files_ascentlint_waiver)
+ - tool_veriblelint ? (files_veriblelint_waiver)
+ - files_rtl
+ toplevel: axi2sramcrs
+
+ lint:
+ <<: *default_target
+ default_tool: verilator
+ parameters:
+ - SYNTHESIS=true
+ tools:
+ verilator:
+ mode: lint-only
+ verilator_options:
+ - "-Wall"
diff --git a/axi2sramcrs/axi2sramcrs_include.core b/axi2sramcrs/axi2sramcrs_include.core
new file mode 100644
index 0000000..7521cce
--- /dev/null
+++ b/axi2sramcrs/axi2sramcrs_include.core
@@ -0,0 +1,46 @@
+CAPI=2:
+# Copyright 2023 Google LLC
+# Copyright 2023 Vivante Corporation
+# Copyright lowRISC contributors.
+# Licensed under the Apache License, Version 2.0, see LICENSE for details.
+# SPDX-License-Identifier: Apache-2.0
+
+name: "vsi:axi2sramcrs:includes:0.1"
+description: "axi2sramcrs includes"
+filesets:
+ files_rtl:
+ files:
+ - rtl/share/Axi_undefs.v : {is_include_file : true}
+ - rtl/share/Axi.v : {is_include_file : true}
+ - rtl/share/axi_slice/defs_axi_slice.v : {is_include_file : true}
+ - rtl/share/axi_slice/undefs_axi_slice.v : {is_include_file : true}
+ file_type: systemVerilogSource
+
+ files_verilator_waiver:
+ depend:
+ # common waivers
+ - lowrisc:lint:common
+ files:
+ - lint/axi2sramcrs.vlt
+ file_type: vlt
+
+ files_ascentlint_waiver:
+ depend:
+ # common waivers
+ - lowrisc:lint:common
+ files:
+ - lint/axi2sramcrs.waiver
+ file_type: waiver
+
+ files_veriblelint_waiver:
+ depend:
+ # common waivers
+ - lowrisc:lint:common
+
+targets:
+ default:
+ filesets:
+ - tool_verilator ? (files_verilator_waiver)
+ - tool_ascentlint ? (files_ascentlint_waiver)
+ - tool_veriblelint ? (files_veriblelint_waiver)
+ - files_rtl
diff --git a/axi2sramcrs/lint/axi2sramcrs.vlt b/axi2sramcrs/lint/axi2sramcrs.vlt
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/axi2sramcrs/lint/axi2sramcrs.vlt
diff --git a/axi2sramcrs/lint/axi2sramcrs.waiver b/axi2sramcrs/lint/axi2sramcrs.waiver
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/axi2sramcrs/lint/axi2sramcrs.waiver
diff --git a/ispyocto/BUILD b/ispyocto/BUILD
new file mode 100644
index 0000000..0f51650
--- /dev/null
+++ b/ispyocto/BUILD
@@ -0,0 +1,8 @@
+# Copyright 2023 Google LLC
+# Copyright 2023 Vivante Corporation
+# Licensed under the Apache License, Version 2.0, see LICENSE for details.
+# SPDX-License-Identifier: Apache-2.0
+
+package(default_visibility = ["//visibility:public"])
+
+exports_files(["BUILD"])
diff --git a/ispyocto/isp_includes.core b/ispyocto/isp_includes.core
new file mode 100644
index 0000000..8e48171
--- /dev/null
+++ b/ispyocto/isp_includes.core
@@ -0,0 +1,52 @@
+CAPI=2:
+# Copyright 2023 Google LLC
+# Copyright 2023 Vivante Corporation
+# Copyright lowRISC contributors.
+# Licensed under the Apache License, Version 2.0, see LICENSE for details.
+# SPDX-License-Identifier: Apache-2.0
+
+name: "vsi:ispyocto:includes:0.1"
+description: "ISP includes"
+filesets:
+ files_rtl:
+ files:
+ - rtl/inc/vsisp_AQ_timescale.vh : {is_include_file : true}
+ - rtl/inc/vsisp_f_sqrt_8bit.vh : {is_include_file : true}
+ - rtl/inc/vsisp_gc_allDefinesForBench.vh : {is_include_file : true}
+ - rtl/inc/vsisp_isp.vh : {is_include_file : true}
+ - rtl/inc/vsisp_jpeg_r2b.vh : {is_include_file : true}
+ - rtl/inc/vsisp_marvin_ctrl.vh : {is_include_file : true}
+ - rtl/inc/vsisp_marvin_id.vh : {is_include_file : true}
+ - rtl/inc/vsisp_marvin_mi.vh : {is_include_file : true}
+ - rtl/inc/vsisp_ram_sizes.vh : {is_include_file : true}
+ - rtl/inc/vsisp_self_resize.vh : {is_include_file : true}
+ file_type: systemVerilogSource
+
+ files_verilator_waiver:
+ depend:
+ # common waivers
+ - lowrisc:lint:common
+ files:
+ - lint/ispyocto.vlt
+ file_type: vlt
+
+ files_ascentlint_waiver:
+ depend:
+ # common waivers
+ - lowrisc:lint:common
+ files:
+ - lint/ispyocto.waiver
+ file_type: waiver
+
+ files_veriblelint_waiver:
+ depend:
+ # common waivers
+ - lowrisc:lint:common
+
+targets:
+ default:
+ filesets:
+ - tool_verilator ? (files_verilator_waiver)
+ - tool_ascentlint ? (files_ascentlint_waiver)
+ - tool_veriblelint ? (files_veriblelint_waiver)
+ - files_rtl
diff --git a/ispyocto/ispyocto.core b/ispyocto/ispyocto.core
new file mode 100644
index 0000000..7e35884
--- /dev/null
+++ b/ispyocto/ispyocto.core
@@ -0,0 +1,202 @@
+CAPI=2:
+# Copyright 2023 Google LLC
+# Copyright 2023 Vivante Corporation
+# Copyright lowRISC contributors.
+# Licensed under the Apache License, Version 2.0, see LICENSE for details.
+# SPDX-License-Identifier: Apache-2.0
+name: "vsi:ip:ispyocto:0.1"
+description: "ispyocto"
+filesets:
+ files_rtl:
+ depend:
+ - vsi:ispyocto:includes
+ files:
+ - rtl/ispyocto/vsisp_add_h_end.v
+ - rtl/ispyocto/vsisp_ahb2pvci.v
+ - rtl/ispyocto/vsisp_AQSync.v
+ - rtl/ispyocto/vsisp_bvci2axi_wr.v
+ - rtl/ispyocto/vsisp_CLOCKGATER.v
+ - rtl/ispyocto/vsisp_conv_422to444.v
+ - rtl/ispyocto/vsisp_conv_dpsbe.v
+ - rtl/ispyocto/vsisp_conv_dpsfe.v
+ - rtl/ispyocto/vsisp_conv_dpsfifo.v
+ - rtl/ispyocto/vsisp_conv_gen_streaming_interface.v
+ - rtl/ispyocto/vsisp_conv.v
+ - rtl/ispyocto/vsisp_conv_yuv2rgb.v
+ - rtl/ispyocto/vsisp_dreg_en_1d.v
+ - rtl/ispyocto/vsisp_dreg_en_2d.v
+ - rtl/ispyocto/vsisp_fifo4fe.v
+ - rtl/ispyocto/vsisp_fifo.v
+ - rtl/ispyocto/vsisp_GC_CG_MOD.v
+ - rtl/ispyocto/vsisp_gc_den_reg.v
+ - rtl/ispyocto/vsisp_gc_dr_reg.v
+ - rtl/ispyocto/vsisp_isp_422_conv.v
+ - rtl/ispyocto/vsisp_isp_awb_acc.v
+ - rtl/ispyocto/vsisp_isp_awb_div.v
+ - rtl/ispyocto/vsisp_isp_awb_meas.v
+ - rtl/ispyocto/vsisp_isp_awb_th.v
+ - rtl/ispyocto/vsisp_isp_awb_wnd.v
+ - rtl/ispyocto/vsisp_isp_bls_regs.v
+ - rtl/ispyocto/vsisp_isp_bls_subtr.v
+ - rtl/ispyocto/vsisp_isp_bls_v2.v
+ - rtl/ispyocto/vsisp_isp_cac_ctrl.v
+ - rtl/ispyocto/vsisp_isp_cac_delay.v
+ - rtl/ispyocto/vsisp_isp_cac_hor_buf.v
+ - rtl/ispyocto/vsisp_isp_cac_hor.v
+ - rtl/ispyocto/vsisp_isp_cac_ver.v
+ - rtl/ispyocto/vsisp_isp_cross_talk.v
+ - rtl/ispyocto/vsisp_isp_crt_tri_mul_add.v
+ - rtl/ispyocto/vsisp_isp_csm_fix.v
+ - rtl/ispyocto/vsisp_isp_csm_tri_mul_add.v
+ - rtl/ispyocto/vsisp_isp_csm.v
+ - rtl/ispyocto/vsisp_isp_demosaic_3x2.v
+ - rtl/ispyocto/vsisp_isp_demosaic_3x3_crcb.v
+ - rtl/ispyocto/vsisp_isp_demosaic5x.v
+ - rtl/ispyocto/vsisp_isp_demosaic_buf_5lines.v
+ - rtl/ispyocto/vsisp_isp_demosaic_dpsbe.v
+ - rtl/ispyocto/vsisp_isp_digi_gain.v
+ - rtl/ispyocto/vsisp_isp_dpsfe.v
+ - rtl/ispyocto/vsisp_isp_exp_ctrl.v
+ - rtl/ispyocto/vsisp_isp_exp_regs.v
+ - rtl/ispyocto/vsisp_isp_exp.v
+ - rtl/ispyocto/vsisp_isp_filt_chr_buf.v
+ - rtl/ispyocto/vsisp_isp_filt_chr_core.v
+ - rtl/ispyocto/vsisp_isp_filt_ctrl.v
+ - rtl/ispyocto/vsisp_isp_filt_hp_core.v
+ - rtl/ispyocto/vsisp_isp_filt_lp_core.v
+ - rtl/ispyocto/vsisp_isp_filt_out_mux.v
+ - rtl/ispyocto/vsisp_isp_filt_regs.v
+ - rtl/ispyocto/vsisp_isp_filt_txtdet.v
+ - rtl/ispyocto/vsisp_isp_filt.v
+ - rtl/ispyocto/vsisp_isp_gamma_channel_fix.v
+ - rtl/ispyocto/vsisp_isp_gamma_out.v
+ - rtl/ispyocto/vsisp_isp_inform.v
+ - rtl/ispyocto/vsisp_isp_irq_handler.v
+ - rtl/ispyocto/vsisp_isp_isp_fifo_wrapper.v
+ - rtl/ispyocto/vsisp_isp_isp_ram_wrapper.v
+ - rtl/ispyocto/vsisp_isp_line_mem_if.v
+ - rtl/ispyocto/vsisp_isp_miv1_mp_sramy_wrapper.v
+ - rtl/ispyocto/vsisp_isp_outform.v
+ - rtl/ispyocto/vsisp_isp_pseudo_random_gen.v
+ - rtl/ispyocto/vsisp_isp_regs.v
+ - rtl/ispyocto/vsisp_isp_rgb_yuv_sel.v
+ - rtl/ispyocto/vsisp_isp_srsz_c_wrapper.v
+ - rtl/ispyocto/vsisp_isp_srsz_y_wrapper.v
+ - rtl/ispyocto/vsisp_isp_tpg_cfg.v
+ - rtl/ispyocto/vsisp_isp.v
+ - rtl/ispyocto/vsisp_m4_clock_gating.v
+ - rtl/ispyocto/vsisp_marvin_ctrl_pvcidis.v
+ - rtl/ispyocto/vsisp_marvin_ctrl_pvci.v
+ - rtl/ispyocto/vsisp_marvin_ctrl_reset_gen.v
+ - rtl/ispyocto/vsisp_marvin_ctrl.v
+ - rtl/ispyocto/vsisp_marvin_dpsfe.v
+ - rtl/ispyocto/vsisp_marvin_dpsfifo.v
+ - rtl/ispyocto/vsisp_marvin_irq_handler.v
+ - rtl/ispyocto/vsisp_marvin_mi_2to3.v
+ - rtl/ispyocto/vsisp_marvin_mi_bp.v
+ - rtl/ispyocto/vsisp_marvin_mi_dpsbe.v
+ - rtl/ispyocto/vsisp_marvin_mi_fifo_bp.v
+ - rtl/ispyocto/vsisp_marvin_mi_fifo.v
+ - rtl/ispyocto/vsisp_marvin_mi_handshake.v
+ - rtl/ispyocto/vsisp_marvin_mi_in_distrib.v
+ - rtl/ispyocto/vsisp_marvin_mi_in.v
+ - rtl/ispyocto/vsisp_marvin_mi_out_addrgen_mp.v
+ - rtl/ispyocto/vsisp_marvin_mi_out_addrgen_sp.v
+ - rtl/ispyocto/vsisp_marvin_mi_out_arbit_mp.v
+ - rtl/ispyocto/vsisp_marvin_mi_out_arbit_sp.v
+ - rtl/ispyocto/vsisp_marvin_mi_out_bp.v
+ - rtl/ispyocto/vsisp_marvin_mi_out_ctrl_mp.v
+ - rtl/ispyocto/vsisp_marvin_mi_out_ctrl_sp.v
+ - rtl/ispyocto/vsisp_marvin_mi_out_mp.v
+ - rtl/ispyocto/vsisp_marvin_mi_out_sp.v
+ - rtl/ispyocto/vsisp_marvin_mi_out_updlogic_mp.v
+ - rtl/ispyocto/vsisp_marvin_mi_out_updlogic_sp.v
+ - rtl/ispyocto/vsisp_marvin_mi_out.v
+ - rtl/ispyocto/vsisp_marvin_mi_regs.v
+ - rtl/ispyocto/vsisp_marvin_mi_swap.v
+ - rtl/ispyocto/vsisp_marvin_mi.v
+ - rtl/ispyocto/vsisp_marvin_pvci_reg_stage.v
+ - rtl/ispyocto/vsisp_marvin_top_a.v
+ - rtl/ispyocto/VSISP_MARVIN_TOP_X.v
+ - rtl/ispyocto/vsisp_mi_bayer_split.v
+ - rtl/ispyocto/vsisp_mi_dp_outstage.v
+ - rtl/ispyocto/vsisp_mi_dp_raw.v
+ - rtl/ispyocto/vsisp_mi_fifo_core.v
+ - rtl/ispyocto/vsisp_mi_fifo_ram.v
+ - rtl/ispyocto/vsisp_mi_jpeg_ctrl.v
+ - rtl/ispyocto/vsisp_pvci_mux.v
+ - rtl/ispyocto/vsisp_pvci_sync.v
+ - rtl/ispyocto/vsisp_resize_conv_ctrl.v
+ - rtl/ispyocto/vsisp_resize_conv.v
+ - rtl/ispyocto/vsisp_resize_to_conv_2to3.v
+ - rtl/ispyocto/vsisp_self_hor_c_scale.v
+ - rtl/ispyocto/vsisp_self_hor_mult.v
+ - rtl/ispyocto/vsisp_self_hor_scale.v
+ - rtl/ispyocto/vsisp_self_resize_c_scale.v
+ - rtl/ispyocto/vsisp_self_resize_scale.v
+ - rtl/ispyocto/vsisp_self_resize.v
+ - rtl/ispyocto/vsisp_self_rsz_dpsbe.v
+ - rtl/ispyocto/vsisp_self_vert_mult.v
+ - rtl/ispyocto/vsisp_self_vert_scale.v
+ - rtl/ispyocto/vsisp_sensor_fifo.v
+ - rtl/ispyocto/vsisp_sync_fifo_core.v
+ - rtl/ispyocto/vsisp_sync_fifo_outp.v
+ - rtl/ispyocto/vsisp_sync_fifo_reset_gen_rd.v
+ - rtl/ispyocto/vsisp_sync_fifo_reset_gen_wr.v
+ - rtl/ispyocto/vsisp_vs_marvin_ramshell.v
+ - rtl/ispyocto/vsisp_yc_split.v
+ - rtl/rams/vsisp_RAM1P128W28B_SS.v
+ - rtl/rams/vsisp_RAM1P320W168B_SS.v
+ - rtl/rams/vsisp_RAM1P320W32B_SS.v
+ - rtl/rams/vsisp_RAM1P80W66B_SS.v
+ file_type: systemVerilogSource
+
+ files_verilator_waiver:
+ depend:
+ # common waivers
+ - lowrisc:lint:common
+ - lowrisc:lint:comportable
+ files:
+ - lint/ispyocto.vlt
+ file_type: vlt
+
+ files_ascentlint_waiver:
+ depend:
+ # common waivers
+ - lowrisc:lint:common
+ - lowrisc:lint:comportable
+ files:
+ - lint/ispyocto.waiver
+ file_type: waiver
+
+ files_veriblelint_waiver:
+ depend:
+ # common waivers
+ - lowrisc:lint:common
+ - lowrisc:lint:comportable
+
+parameters:
+ SYNTHESIS:
+ datatype: bool
+ paramtype: vlogdefine
+
+
+targets:
+ default: &default_target
+ filesets:
+ - tool_verilator ? (files_verilator_waiver)
+ - tool_ascentlint ? (files_ascentlint_waiver)
+ - tool_veriblelint ? (files_veriblelint_waiver)
+ - files_rtl
+ toplevel: vsisp
+
+ lint:
+ <<: *default_target
+ default_tool: verilator
+ parameters:
+ - SYNTHESIS=true
+ tools:
+ verilator:
+ mode: lint-only
+ verilator_options:
+ - "-Wall"
diff --git a/ispyocto/lint/ispyocto.vlt b/ispyocto/lint/ispyocto.vlt
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/ispyocto/lint/ispyocto.vlt
diff --git a/ispyocto/rtl/inc/vsisp_AQ_timescale.vh b/ispyocto/rtl/inc/vsisp_AQ_timescale.vh
index 7c100af..71c5802 100644
--- a/ispyocto/rtl/inc/vsisp_AQ_timescale.vh
+++ b/ispyocto/rtl/inc/vsisp_AQ_timescale.vh
@@ -19,4 +19,4 @@
//
//****************************************************************************
-`timescale 1ps / 1ps
+`timescale 1ns / 1ps
diff --git a/ispyocto/rtl/isp8000_filelist.txt b/ispyocto/rtl/isp8000_filelist.txt
deleted file mode 100644
index 857da62..0000000
--- a/ispyocto/rtl/isp8000_filelist.txt
+++ /dev/null
@@ -1,140 +0,0 @@
-+incdir+./inc
-isp8000/vsisp_add_h_end.v
-isp8000/vsisp_ahb2pvci.v
-isp8000/vsisp_AQSync.v
-isp8000/vsisp_bvci2axi_wr.v
-isp8000/vsisp_CLOCKGATER.v
-isp8000/vsisp_conv_422to444.v
-isp8000/vsisp_conv_dpsbe.v
-isp8000/vsisp_conv_dpsfe.v
-isp8000/vsisp_conv_dpsfifo.v
-isp8000/vsisp_conv_gen_streaming_interface.v
-isp8000/vsisp_conv.v
-isp8000/vsisp_conv_yuv2rgb.v
-isp8000/vsisp_dreg_en_1d.v
-isp8000/vsisp_dreg_en_2d.v
-isp8000/vsisp_fifo4fe.v
-isp8000/vsisp_fifo.v
-isp8000/vsisp_GC_CG_MOD.v
-isp8000/vsisp_gc_den_reg.v
-isp8000/vsisp_gc_dr_reg.v
-isp8000/vsisp_isp_422_conv.v
-isp8000/vsisp_isp_awb_acc.v
-isp8000/vsisp_isp_awb_div.v
-isp8000/vsisp_isp_awb_meas.v
-isp8000/vsisp_isp_awb_th.v
-isp8000/vsisp_isp_awb_wnd.v
-isp8000/vsisp_isp_bls_regs.v
-isp8000/vsisp_isp_bls_subtr.v
-isp8000/vsisp_isp_bls_v2.v
-isp8000/vsisp_isp_cac_ctrl.v
-isp8000/vsisp_isp_cac_delay.v
-isp8000/vsisp_isp_cac_hor_buf.v
-isp8000/vsisp_isp_cac_hor.v
-isp8000/vsisp_isp_cac_ver.v
-isp8000/vsisp_isp_cross_talk.v
-isp8000/vsisp_isp_crt_tri_mul_add.v
-isp8000/vsisp_isp_csm_fix.v
-isp8000/vsisp_isp_csm_tri_mul_add.v
-isp8000/vsisp_isp_csm.v
-isp8000/vsisp_isp_demosaic_3x2.v
-isp8000/vsisp_isp_demosaic_3x3_crcb.v
-isp8000/vsisp_isp_demosaic5x.v
-isp8000/vsisp_isp_demosaic_buf_5lines.v
-isp8000/vsisp_isp_demosaic_dpsbe.v
-isp8000/vsisp_isp_digi_gain.v
-isp8000/vsisp_isp_dpsfe.v
-isp8000/vsisp_isp_exp_ctrl.v
-isp8000/vsisp_isp_exp_regs.v
-isp8000/vsisp_isp_exp.v
-isp8000/vsisp_isp_filt_chr_buf.v
-isp8000/vsisp_isp_filt_chr_core.v
-isp8000/vsisp_isp_filt_ctrl.v
-isp8000/vsisp_isp_filt_hp_core.v
-isp8000/vsisp_isp_filt_lp_core.v
-isp8000/vsisp_isp_filt_out_mux.v
-isp8000/vsisp_isp_filt_regs.v
-isp8000/vsisp_isp_filt_txtdet.v
-isp8000/vsisp_isp_filt.v
-isp8000/vsisp_isp_gamma_channel_fix.v
-isp8000/vsisp_isp_gamma_out.v
-isp8000/vsisp_isp_inform.v
-isp8000/vsisp_isp_irq_handler.v
-isp8000/vsisp_isp_isp_fifo_wrapper.v
-isp8000/vsisp_isp_isp_ram_wrapper.v
-isp8000/vsisp_isp_line_mem_if.v
-isp8000/vsisp_isp_miv1_mp_sramy_wrapper.v
-isp8000/vsisp_isp_outform.v
-isp8000/vsisp_isp_pseudo_random_gen.v
-isp8000/vsisp_isp_regs.v
-isp8000/vsisp_isp_rgb_yuv_sel.v
-isp8000/vsisp_isp_srsz_c_wrapper.v
-isp8000/vsisp_isp_srsz_y_wrapper.v
-isp8000/vsisp_isp_tpg_cfg.v
-isp8000/vsisp_isp.v
-isp8000/vsisp_m4_clock_gating.v
-isp8000/vsisp_marvin_ctrl_pvcidis.v
-isp8000/vsisp_marvin_ctrl_pvci.v
-isp8000/vsisp_marvin_ctrl_reset_gen.v
-isp8000/vsisp_marvin_ctrl.v
-isp8000/vsisp_marvin_dpsfe.v
-isp8000/vsisp_marvin_dpsfifo.v
-isp8000/vsisp_marvin_irq_handler.v
-isp8000/vsisp_marvin_mi_2to3.v
-isp8000/vsisp_marvin_mi_bp.v
-isp8000/vsisp_marvin_mi_dpsbe.v
-isp8000/vsisp_marvin_mi_fifo_bp.v
-isp8000/vsisp_marvin_mi_fifo.v
-isp8000/vsisp_marvin_mi_handshake.v
-isp8000/vsisp_marvin_mi_in_distrib.v
-isp8000/vsisp_marvin_mi_in.v
-isp8000/vsisp_marvin_mi_out_addrgen_mp.v
-isp8000/vsisp_marvin_mi_out_addrgen_sp.v
-isp8000/vsisp_marvin_mi_out_arbit_mp.v
-isp8000/vsisp_marvin_mi_out_arbit_sp.v
-isp8000/vsisp_marvin_mi_out_bp.v
-isp8000/vsisp_marvin_mi_out_ctrl_mp.v
-isp8000/vsisp_marvin_mi_out_ctrl_sp.v
-isp8000/vsisp_marvin_mi_out_mp.v
-isp8000/vsisp_marvin_mi_out_sp.v
-isp8000/vsisp_marvin_mi_out_updlogic_mp.v
-isp8000/vsisp_marvin_mi_out_updlogic_sp.v
-isp8000/vsisp_marvin_mi_out.v
-isp8000/vsisp_marvin_mi_regs.v
-isp8000/vsisp_marvin_mi_swap.v
-isp8000/vsisp_marvin_mi.v
-isp8000/vsisp_marvin_pvci_reg_stage.v
-isp8000/vsisp_marvin_top_a.v
-isp8000/VSISP_MARVIN_TOP_X.v
-isp8000/vsisp_mi_bayer_split.v
-isp8000/vsisp_mi_dp_outstage.v
-isp8000/vsisp_mi_dp_raw.v
-isp8000/vsisp_mi_fifo_core.v
-isp8000/vsisp_mi_fifo_ram.v
-isp8000/vsisp_mi_jpeg_ctrl.v
-isp8000/vsisp_pvci_mux.v
-isp8000/vsisp_pvci_sync.v
-isp8000/vsisp_resize_conv_ctrl.v
-isp8000/vsisp_resize_conv.v
-isp8000/vsisp_resize_to_conv_2to3.v
-isp8000/vsisp_self_hor_c_scale.v
-isp8000/vsisp_self_hor_mult.v
-isp8000/vsisp_self_hor_scale.v
-isp8000/vsisp_self_resize_c_scale.v
-isp8000/vsisp_self_resize_scale.v
-isp8000/vsisp_self_resize.v
-isp8000/vsisp_self_rsz_dpsbe.v
-isp8000/vsisp_self_vert_mult.v
-isp8000/vsisp_self_vert_scale.v
-isp8000/vsisp_sensor_fifo.v
-isp8000/vsisp_sync_fifo_core.v
-isp8000/vsisp_sync_fifo_outp.v
-isp8000/vsisp_sync_fifo_reset_gen_rd.v
-isp8000/vsisp_sync_fifo_reset_gen_wr.v
-isp8000/vsisp_vs_marvin_ramshell.v
-isp8000/vsisp_yc_split.v
-rams/vsisp_RAM1P128W28B_SS.v
-rams/vsisp_RAM1P320W168B_SS.v
-rams/vsisp_RAM1P320W32B_SS.v
-rams/vsisp_RAM1P80W66B_SS.v
-undef/vsisp_vsi_undef.v
diff --git a/ispyocto/rtl/ispyocto/vsisp_isp_isp_fifo_wrapper.v b/ispyocto/rtl/ispyocto/vsisp_isp_isp_fifo_wrapper.v
index ca79571..c5d6dc9 100644
--- a/ispyocto/rtl/ispyocto/vsisp_isp_isp_fifo_wrapper.v
+++ b/ispyocto/rtl/ispyocto/vsisp_isp_isp_fifo_wrapper.v
@@ -31,50 +31,6 @@
input wEn0_;
output [28-1:0] rData0;
wire [28-1:0] rData0;
- `ifdef FPGA
- reg [71:0] fpgaWData_0_0;
- wire [71:0] fpgaRData_0_0;
- always @(wData0[27:0])
- fpgaWData_0_0 = 72'd0 | wData0[27:0];
- wire [71:0] fpgaRData_0_0_0;
- assign rData0[27:0] = fpgaRData_0_0_0[28-1:0];
- wire wEn0Stack_0_0_0_ = wEn0_;
- `ifdef FPGA_ALTERA
- FPGA_ALTERA_RF2P512W72B ram_0_0_0 (
- .address_a ({2'd0,rwAddr0}),
- .address_b ({2'd0,rwAddr0}),
- .clock_a (rwclk0),
- .clock_b (rwclk0),
- .data_a (72'b0),
- .data_b (fpgaWData_0_0[71:0]),
- .rden_a (~cEn0_ && (cEn0_|wEn0_)),
- .rden_b (1'b0),
- .wren_a (1'b0),
- .wren_b (~(cEn0_|wEn0_)),
- .q_a (fpgaRData_0_0_0[71:0]),
- .q_b ());
- `else
- FPGA_RF2P512W72B ram_0_0_0 (
- .DOA (fpgaRData_0_0_0[63:0]),
- .DOPA (fpgaRData_0_0_0[71:64]),
- .DOB (),
- .DOPB (),
- .ADDRA ({2'd0,rwAddr0}),
- .DIA (64'd0),
- .DIPA (8'd0),
- .ENA (~cEn0_ && (cEn0_|wEn0_)),
- .CLKA (rwclk0),
- .SSRA (1'b0),
- .WEA (2'd0),
- .ADDRB ({2'd0,rwAddr0}),
- .DIB (fpgaWData_0_0[63:0]),
- .DIPB (fpgaWData_0_0[71:64]),
- .ENB (~(cEn0_|wEn0_)),
- .CLKB (rwclk0),
- .SSRB (1'b0),
- .WEB ({~(cEn0_|wEn0_),~(cEn0_|wEn0_)}));
- `endif
- `else
`ifdef OLD_MEM_MODEL
`else
`ifdef AQ_TSMC28HPM_RAM_MODEL
@@ -233,7 +189,6 @@
`endif
`endif
`endif
- `endif
`ifdef VIVANTE_CHECK_RAM_USAGE
`ifdef VIVANTE_SIM_END
reg [1-1:0] writeHappened;
diff --git a/ispyocto/rtl/ispyocto/vsisp_isp_isp_ram_wrapper.v b/ispyocto/rtl/ispyocto/vsisp_isp_isp_ram_wrapper.v
index 776b9ed..c865b95 100644
--- a/ispyocto/rtl/ispyocto/vsisp_isp_isp_ram_wrapper.v
+++ b/ispyocto/rtl/ispyocto/vsisp_isp_isp_ram_wrapper.v
@@ -31,134 +31,6 @@
input wEn0_;
output [168-1:0] rData0;
wire [168-1:0] rData0;
- `ifdef FPGA
- reg [71:0] fpgaWData_0_0;
- wire [71:0] fpgaRData_0_0;
- always @(wData0[71:0])
- fpgaWData_0_0 = 72'd0 | wData0[71:0];
- wire [71:0] fpgaRData_0_0_0;
- assign rData0[71:0] = fpgaRData_0_0_0[72-1:0];
- wire wEn0Stack_0_0_0_ = wEn0_;
- `ifdef FPGA_ALTERA
- FPGA_ALTERA_RF2P512W72B ram_0_0_0 (
- .address_a ({rwAddr0}),
- .address_b ({rwAddr0}),
- .clock_a (rwclk0),
- .clock_b (rwclk0),
- .data_a (72'b0),
- .data_b (fpgaWData_0_0[71:0]),
- .rden_a (~cEn0_ && (cEn0_|wEn0_)),
- .rden_b (1'b0),
- .wren_a (1'b0),
- .wren_b (~(cEn0_|wEn0_)),
- .q_a (fpgaRData_0_0_0[71:0]),
- .q_b ());
- `else
- FPGA_RF2P512W72B ram_0_0_0 (
- .DOA (fpgaRData_0_0_0[63:0]),
- .DOPA (fpgaRData_0_0_0[71:64]),
- .DOB (),
- .DOPB (),
- .ADDRA ({rwAddr0}),
- .DIA (64'd0),
- .DIPA (8'd0),
- .ENA (~cEn0_ && (cEn0_|wEn0_)),
- .CLKA (rwclk0),
- .SSRA (1'b0),
- .WEA (2'd0),
- .ADDRB ({rwAddr0}),
- .DIB (fpgaWData_0_0[63:0]),
- .DIPB (fpgaWData_0_0[71:64]),
- .ENB (~(cEn0_|wEn0_)),
- .CLKB (rwclk0),
- .SSRB (1'b0),
- .WEB ({~(cEn0_|wEn0_),~(cEn0_|wEn0_)}));
- `endif
- reg [71:0] fpgaWData_0_1;
- wire [71:0] fpgaRData_0_1;
- always @(wData0[143:72])
- fpgaWData_0_1 = 72'd0 | wData0[143:72];
- wire [71:0] fpgaRData_0_1_0;
- assign rData0[143:72] = fpgaRData_0_1_0[72-1:0];
- wire wEn0Stack_0_1_0_ = wEn0_;
- `ifdef FPGA_ALTERA
- FPGA_ALTERA_RF2P512W72B ram_0_1_0 (
- .address_a ({rwAddr0}),
- .address_b ({rwAddr0}),
- .clock_a (rwclk0),
- .clock_b (rwclk0),
- .data_a (72'b0),
- .data_b (fpgaWData_0_1[71:0]),
- .rden_a (~cEn0_ && (cEn0_|wEn0_)),
- .rden_b (1'b0),
- .wren_a (1'b0),
- .wren_b (~(cEn0_|wEn0_)),
- .q_a (fpgaRData_0_1_0[71:0]),
- .q_b ());
- `else
- FPGA_RF2P512W72B ram_0_1_0 (
- .DOA (fpgaRData_0_1_0[63:0]),
- .DOPA (fpgaRData_0_1_0[71:64]),
- .DOB (),
- .DOPB (),
- .ADDRA ({rwAddr0}),
- .DIA (64'd0),
- .DIPA (8'd0),
- .ENA (~cEn0_ && (cEn0_|wEn0_)),
- .CLKA (rwclk0),
- .SSRA (1'b0),
- .WEA (2'd0),
- .ADDRB ({rwAddr0}),
- .DIB (fpgaWData_0_1[63:0]),
- .DIPB (fpgaWData_0_1[71:64]),
- .ENB (~(cEn0_|wEn0_)),
- .CLKB (rwclk0),
- .SSRB (1'b0),
- .WEB ({~(cEn0_|wEn0_),~(cEn0_|wEn0_)}));
- `endif
- reg [71:0] fpgaWData_0_2;
- wire [71:0] fpgaRData_0_2;
- always @(wData0[167:144])
- fpgaWData_0_2 = 72'd0 | wData0[167:144];
- wire [71:0] fpgaRData_0_2_0;
- assign rData0[167:144] = fpgaRData_0_2_0[24-1:0];
- wire wEn0Stack_0_2_0_ = wEn0_;
- `ifdef FPGA_ALTERA
- FPGA_ALTERA_RF2P512W72B ram_0_2_0 (
- .address_a ({rwAddr0}),
- .address_b ({rwAddr0}),
- .clock_a (rwclk0),
- .clock_b (rwclk0),
- .data_a (72'b0),
- .data_b (fpgaWData_0_2[71:0]),
- .rden_a (~cEn0_ && (cEn0_|wEn0_)),
- .rden_b (1'b0),
- .wren_a (1'b0),
- .wren_b (~(cEn0_|wEn0_)),
- .q_a (fpgaRData_0_2_0[71:0]),
- .q_b ());
- `else
- FPGA_RF2P512W72B ram_0_2_0 (
- .DOA (fpgaRData_0_2_0[63:0]),
- .DOPA (fpgaRData_0_2_0[71:64]),
- .DOB (),
- .DOPB (),
- .ADDRA ({rwAddr0}),
- .DIA (64'd0),
- .DIPA (8'd0),
- .ENA (~cEn0_ && (cEn0_|wEn0_)),
- .CLKA (rwclk0),
- .SSRA (1'b0),
- .WEA (2'd0),
- .ADDRB ({rwAddr0}),
- .DIB (fpgaWData_0_2[63:0]),
- .DIPB (fpgaWData_0_2[71:64]),
- .ENB (~(cEn0_|wEn0_)),
- .CLKB (rwclk0),
- .SSRB (1'b0),
- .WEB ({~(cEn0_|wEn0_),~(cEn0_|wEn0_)}));
- `endif
- `else
`ifdef OLD_MEM_MODEL
`else
`ifdef AQ_TSMC28HPM_RAM_MODEL
@@ -411,7 +283,6 @@
`endif
`endif
`endif
- `endif
`ifdef VIVANTE_CHECK_RAM_USAGE
`ifdef VIVANTE_SIM_END
reg [1-1:0] writeHappened;
diff --git a/ispyocto/rtl/ispyocto/vsisp_isp_miv1_mp_sramy_wrapper.v b/ispyocto/rtl/ispyocto/vsisp_isp_miv1_mp_sramy_wrapper.v
index 928614e..c33db22 100644
--- a/ispyocto/rtl/ispyocto/vsisp_isp_miv1_mp_sramy_wrapper.v
+++ b/ispyocto/rtl/ispyocto/vsisp_isp_miv1_mp_sramy_wrapper.v
@@ -31,50 +31,6 @@
input wEn0_;
output [66-1:0] rData0;
wire [66-1:0] rData0;
- `ifdef FPGA
- reg [71:0] fpgaWData_0_0;
- wire [71:0] fpgaRData_0_0;
- always @(wData0[65:0])
- fpgaWData_0_0 = 72'd0 | wData0[65:0];
- wire [71:0] fpgaRData_0_0_0;
- assign rData0[65:0] = fpgaRData_0_0_0[66-1:0];
- wire wEn0Stack_0_0_0_ = wEn0_;
- `ifdef FPGA_ALTERA
- FPGA_ALTERA_RF2P512W72B ram_0_0_0 (
- .address_a ({2'd0,rwAddr0}),
- .address_b ({2'd0,rwAddr0}),
- .clock_a (rwclk0),
- .clock_b (rwclk0),
- .data_a (72'b0),
- .data_b (fpgaWData_0_0[71:0]),
- .rden_a (~cEn0_ && (cEn0_|wEn0_)),
- .rden_b (1'b0),
- .wren_a (1'b0),
- .wren_b (~(cEn0_|wEn0_)),
- .q_a (fpgaRData_0_0_0[71:0]),
- .q_b ());
- `else
- FPGA_RF2P512W72B ram_0_0_0 (
- .DOA (fpgaRData_0_0_0[63:0]),
- .DOPA (fpgaRData_0_0_0[71:64]),
- .DOB (),
- .DOPB (),
- .ADDRA ({2'd0,rwAddr0}),
- .DIA (64'd0),
- .DIPA (8'd0),
- .ENA (~cEn0_ && (cEn0_|wEn0_)),
- .CLKA (rwclk0),
- .SSRA (1'b0),
- .WEA (2'd0),
- .ADDRB ({2'd0,rwAddr0}),
- .DIB (fpgaWData_0_0[63:0]),
- .DIPB (fpgaWData_0_0[71:64]),
- .ENB (~(cEn0_|wEn0_)),
- .CLKB (rwclk0),
- .SSRB (1'b0),
- .WEB ({~(cEn0_|wEn0_),~(cEn0_|wEn0_)}));
- `endif
- `else
`ifdef OLD_MEM_MODEL
`else
`ifdef AQ_TSMC28HPM_RAM_MODEL
@@ -233,7 +189,6 @@
`endif
`endif
`endif
- `endif
`ifdef VIVANTE_CHECK_RAM_USAGE
`ifdef VIVANTE_SIM_END
reg [1-1:0] writeHappened;
diff --git a/ispyocto/rtl/ispyocto/vsisp_isp_srsz_c_wrapper.v b/ispyocto/rtl/ispyocto/vsisp_isp_srsz_c_wrapper.v
index 65a29df..80aa025 100644
--- a/ispyocto/rtl/ispyocto/vsisp_isp_srsz_c_wrapper.v
+++ b/ispyocto/rtl/ispyocto/vsisp_isp_srsz_c_wrapper.v
@@ -31,50 +31,6 @@
input wEn0_;
output [32-1:0] rData0;
wire [32-1:0] rData0;
- `ifdef FPGA
- reg [71:0] fpgaWData_0_0;
- wire [71:0] fpgaRData_0_0;
- always @(wData0[31:0])
- fpgaWData_0_0 = 72'd0 | wData0[31:0];
- wire [71:0] fpgaRData_0_0_0;
- assign rData0[31:0] = fpgaRData_0_0_0[32-1:0];
- wire wEn0Stack_0_0_0_ = wEn0_;
- `ifdef FPGA_ALTERA
- FPGA_ALTERA_RF2P512W72B ram_0_0_0 (
- .address_a ({rwAddr0}),
- .address_b ({rwAddr0}),
- .clock_a (rwclk0),
- .clock_b (rwclk0),
- .data_a (72'b0),
- .data_b (fpgaWData_0_0[71:0]),
- .rden_a (~cEn0_ && (cEn0_|wEn0_)),
- .rden_b (1'b0),
- .wren_a (1'b0),
- .wren_b (~(cEn0_|wEn0_)),
- .q_a (fpgaRData_0_0_0[71:0]),
- .q_b ());
- `else
- FPGA_RF2P512W72B ram_0_0_0 (
- .DOA (fpgaRData_0_0_0[63:0]),
- .DOPA (fpgaRData_0_0_0[71:64]),
- .DOB (),
- .DOPB (),
- .ADDRA ({rwAddr0}),
- .DIA (64'd0),
- .DIPA (8'd0),
- .ENA (~cEn0_ && (cEn0_|wEn0_)),
- .CLKA (rwclk0),
- .SSRA (1'b0),
- .WEA (2'd0),
- .ADDRB ({rwAddr0}),
- .DIB (fpgaWData_0_0[63:0]),
- .DIPB (fpgaWData_0_0[71:64]),
- .ENB (~(cEn0_|wEn0_)),
- .CLKB (rwclk0),
- .SSRB (1'b0),
- .WEB ({~(cEn0_|wEn0_),~(cEn0_|wEn0_)}));
- `endif
- `else
`ifdef OLD_MEM_MODEL
`else
`ifdef AQ_TSMC28HPM_RAM_MODEL
@@ -233,7 +189,6 @@
`endif
`endif
`endif
- `endif
`ifdef VIVANTE_CHECK_RAM_USAGE
`ifdef VIVANTE_SIM_END
reg [1-1:0] writeHappened;
diff --git a/ispyocto/rtl/ispyocto/vsisp_isp_srsz_y_wrapper.v b/ispyocto/rtl/ispyocto/vsisp_isp_srsz_y_wrapper.v
index 8b804a9..ac69eea 100644
--- a/ispyocto/rtl/ispyocto/vsisp_isp_srsz_y_wrapper.v
+++ b/ispyocto/rtl/ispyocto/vsisp_isp_srsz_y_wrapper.v
@@ -31,50 +31,6 @@
input wEn0_;
output [32-1:0] rData0;
wire [32-1:0] rData0;
- `ifdef FPGA
- reg [71:0] fpgaWData_0_0;
- wire [71:0] fpgaRData_0_0;
- always @(wData0[31:0])
- fpgaWData_0_0 = 72'd0 | wData0[31:0];
- wire [71:0] fpgaRData_0_0_0;
- assign rData0[31:0] = fpgaRData_0_0_0[32-1:0];
- wire wEn0Stack_0_0_0_ = wEn0_;
- `ifdef FPGA_ALTERA
- FPGA_ALTERA_RF2P512W72B ram_0_0_0 (
- .address_a ({rwAddr0}),
- .address_b ({rwAddr0}),
- .clock_a (rwclk0),
- .clock_b (rwclk0),
- .data_a (72'b0),
- .data_b (fpgaWData_0_0[71:0]),
- .rden_a (~cEn0_ && (cEn0_|wEn0_)),
- .rden_b (1'b0),
- .wren_a (1'b0),
- .wren_b (~(cEn0_|wEn0_)),
- .q_a (fpgaRData_0_0_0[71:0]),
- .q_b ());
- `else
- FPGA_RF2P512W72B ram_0_0_0 (
- .DOA (fpgaRData_0_0_0[63:0]),
- .DOPA (fpgaRData_0_0_0[71:64]),
- .DOB (),
- .DOPB (),
- .ADDRA ({rwAddr0}),
- .DIA (64'd0),
- .DIPA (8'd0),
- .ENA (~cEn0_ && (cEn0_|wEn0_)),
- .CLKA (rwclk0),
- .SSRA (1'b0),
- .WEA (2'd0),
- .ADDRB ({rwAddr0}),
- .DIB (fpgaWData_0_0[63:0]),
- .DIPB (fpgaWData_0_0[71:64]),
- .ENB (~(cEn0_|wEn0_)),
- .CLKB (rwclk0),
- .SSRB (1'b0),
- .WEB ({~(cEn0_|wEn0_),~(cEn0_|wEn0_)}));
- `endif
- `else
`ifdef OLD_MEM_MODEL
`else
`ifdef AQ_TSMC28HPM_RAM_MODEL
@@ -233,7 +189,6 @@
`endif
`endif
`endif
- `endif
`ifdef VIVANTE_CHECK_RAM_USAGE
`ifdef VIVANTE_SIM_END
reg [1-1:0] writeHappened;
diff --git a/ispyocto/rtl/ispyocto_filelist.txt b/ispyocto/rtl/ispyocto_filelist.txt
new file mode 100644
index 0000000..0e63542
--- /dev/null
+++ b/ispyocto/rtl/ispyocto_filelist.txt
@@ -0,0 +1,140 @@
++incdir+./inc
+ispyocto/vsisp_add_h_end.v
+ispyocto/vsisp_ahb2pvci.v
+ispyocto/vsisp_AQSync.v
+ispyocto/vsisp_bvci2axi_wr.v
+ispyocto/vsisp_CLOCKGATER.v
+ispyocto/vsisp_conv_422to444.v
+ispyocto/vsisp_conv_dpsbe.v
+ispyocto/vsisp_conv_dpsfe.v
+ispyocto/vsisp_conv_dpsfifo.v
+ispyocto/vsisp_conv_gen_streaming_interface.v
+ispyocto/vsisp_conv.v
+ispyocto/vsisp_conv_yuv2rgb.v
+ispyocto/vsisp_dreg_en_1d.v
+ispyocto/vsisp_dreg_en_2d.v
+ispyocto/vsisp_fifo4fe.v
+ispyocto/vsisp_fifo.v
+ispyocto/vsisp_GC_CG_MOD.v
+ispyocto/vsisp_gc_den_reg.v
+ispyocto/vsisp_gc_dr_reg.v
+ispyocto/vsisp_isp_422_conv.v
+ispyocto/vsisp_isp_awb_acc.v
+ispyocto/vsisp_isp_awb_div.v
+ispyocto/vsisp_isp_awb_meas.v
+ispyocto/vsisp_isp_awb_th.v
+ispyocto/vsisp_isp_awb_wnd.v
+ispyocto/vsisp_isp_bls_regs.v
+ispyocto/vsisp_isp_bls_subtr.v
+ispyocto/vsisp_isp_bls_v2.v
+ispyocto/vsisp_isp_cac_ctrl.v
+ispyocto/vsisp_isp_cac_delay.v
+ispyocto/vsisp_isp_cac_hor_buf.v
+ispyocto/vsisp_isp_cac_hor.v
+ispyocto/vsisp_isp_cac_ver.v
+ispyocto/vsisp_isp_cross_talk.v
+ispyocto/vsisp_isp_crt_tri_mul_add.v
+ispyocto/vsisp_isp_csm_fix.v
+ispyocto/vsisp_isp_csm_tri_mul_add.v
+ispyocto/vsisp_isp_csm.v
+ispyocto/vsisp_isp_demosaic_3x2.v
+ispyocto/vsisp_isp_demosaic_3x3_crcb.v
+ispyocto/vsisp_isp_demosaic5x.v
+ispyocto/vsisp_isp_demosaic_buf_5lines.v
+ispyocto/vsisp_isp_demosaic_dpsbe.v
+ispyocto/vsisp_isp_digi_gain.v
+ispyocto/vsisp_isp_dpsfe.v
+ispyocto/vsisp_isp_exp_ctrl.v
+ispyocto/vsisp_isp_exp_regs.v
+ispyocto/vsisp_isp_exp.v
+ispyocto/vsisp_isp_filt_chr_buf.v
+ispyocto/vsisp_isp_filt_chr_core.v
+ispyocto/vsisp_isp_filt_ctrl.v
+ispyocto/vsisp_isp_filt_hp_core.v
+ispyocto/vsisp_isp_filt_lp_core.v
+ispyocto/vsisp_isp_filt_out_mux.v
+ispyocto/vsisp_isp_filt_regs.v
+ispyocto/vsisp_isp_filt_txtdet.v
+ispyocto/vsisp_isp_filt.v
+ispyocto/vsisp_isp_gamma_channel_fix.v
+ispyocto/vsisp_isp_gamma_out.v
+ispyocto/vsisp_isp_inform.v
+ispyocto/vsisp_isp_irq_handler.v
+ispyocto/vsisp_isp_isp_fifo_wrapper.v
+ispyocto/vsisp_isp_isp_ram_wrapper.v
+ispyocto/vsisp_isp_line_mem_if.v
+ispyocto/vsisp_isp_miv1_mp_sramy_wrapper.v
+ispyocto/vsisp_isp_outform.v
+ispyocto/vsisp_isp_pseudo_random_gen.v
+ispyocto/vsisp_isp_regs.v
+ispyocto/vsisp_isp_rgb_yuv_sel.v
+ispyocto/vsisp_isp_srsz_c_wrapper.v
+ispyocto/vsisp_isp_srsz_y_wrapper.v
+ispyocto/vsisp_isp_tpg_cfg.v
+ispyocto/vsisp_isp.v
+ispyocto/vsisp_m4_clock_gating.v
+ispyocto/vsisp_marvin_ctrl_pvcidis.v
+ispyocto/vsisp_marvin_ctrl_pvci.v
+ispyocto/vsisp_marvin_ctrl_reset_gen.v
+ispyocto/vsisp_marvin_ctrl.v
+ispyocto/vsisp_marvin_dpsfe.v
+ispyocto/vsisp_marvin_dpsfifo.v
+ispyocto/vsisp_marvin_irq_handler.v
+ispyocto/vsisp_marvin_mi_2to3.v
+ispyocto/vsisp_marvin_mi_bp.v
+ispyocto/vsisp_marvin_mi_dpsbe.v
+ispyocto/vsisp_marvin_mi_fifo_bp.v
+ispyocto/vsisp_marvin_mi_fifo.v
+ispyocto/vsisp_marvin_mi_handshake.v
+ispyocto/vsisp_marvin_mi_in_distrib.v
+ispyocto/vsisp_marvin_mi_in.v
+ispyocto/vsisp_marvin_mi_out_addrgen_mp.v
+ispyocto/vsisp_marvin_mi_out_addrgen_sp.v
+ispyocto/vsisp_marvin_mi_out_arbit_mp.v
+ispyocto/vsisp_marvin_mi_out_arbit_sp.v
+ispyocto/vsisp_marvin_mi_out_bp.v
+ispyocto/vsisp_marvin_mi_out_ctrl_mp.v
+ispyocto/vsisp_marvin_mi_out_ctrl_sp.v
+ispyocto/vsisp_marvin_mi_out_mp.v
+ispyocto/vsisp_marvin_mi_out_sp.v
+ispyocto/vsisp_marvin_mi_out_updlogic_mp.v
+ispyocto/vsisp_marvin_mi_out_updlogic_sp.v
+ispyocto/vsisp_marvin_mi_out.v
+ispyocto/vsisp_marvin_mi_regs.v
+ispyocto/vsisp_marvin_mi_swap.v
+ispyocto/vsisp_marvin_mi.v
+ispyocto/vsisp_marvin_pvci_reg_stage.v
+ispyocto/vsisp_marvin_top_a.v
+ispyocto/VSISP_MARVIN_TOP_X.v
+ispyocto/vsisp_mi_bayer_split.v
+ispyocto/vsisp_mi_dp_outstage.v
+ispyocto/vsisp_mi_dp_raw.v
+ispyocto/vsisp_mi_fifo_core.v
+ispyocto/vsisp_mi_fifo_ram.v
+ispyocto/vsisp_mi_jpeg_ctrl.v
+ispyocto/vsisp_pvci_mux.v
+ispyocto/vsisp_pvci_sync.v
+ispyocto/vsisp_resize_conv_ctrl.v
+ispyocto/vsisp_resize_conv.v
+ispyocto/vsisp_resize_to_conv_2to3.v
+ispyocto/vsisp_self_hor_c_scale.v
+ispyocto/vsisp_self_hor_mult.v
+ispyocto/vsisp_self_hor_scale.v
+ispyocto/vsisp_self_resize_c_scale.v
+ispyocto/vsisp_self_resize_scale.v
+ispyocto/vsisp_self_resize.v
+ispyocto/vsisp_self_rsz_dpsbe.v
+ispyocto/vsisp_self_vert_mult.v
+ispyocto/vsisp_self_vert_scale.v
+ispyocto/vsisp_sensor_fifo.v
+ispyocto/vsisp_sync_fifo_core.v
+ispyocto/vsisp_sync_fifo_outp.v
+ispyocto/vsisp_sync_fifo_reset_gen_rd.v
+ispyocto/vsisp_sync_fifo_reset_gen_wr.v
+ispyocto/vsisp_vs_marvin_ramshell.v
+ispyocto/vsisp_yc_split.v
+rams/vsisp_RAM1P128W28B_SS.v
+rams/vsisp_RAM1P320W168B_SS.v
+rams/vsisp_RAM1P320W32B_SS.v
+rams/vsisp_RAM1P80W66B_SS.v
+undef/vsisp_vsi_undef.v
