Added axi to tlul translater for ISPYocto Change-Id: I9e9ac139f0e13e821c198cf482eaf86c0e2c9e84
diff --git a/axi2sramcrs/rtl/axi2axilite/axi2axilite.v b/axi2sramcrs/rtl/axi2axilite/axi2axilite.v new file mode 100644 index 0000000..68e4946 --- /dev/null +++ b/axi2sramcrs/rtl/axi2axilite/axi2axilite.v
@@ -0,0 +1,556 @@ +//**************************************************************************** +// +// Copyright 2017-2023 Vivante Corporation +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +//**************************************************************************** +// Auto-generated file on 11/03/2023. +// +//**************************************************************************** + +module axi2axilite + #( + //id width + parameter ARID_WIDTH=4, + parameter AWID_WIDTH=4, + //addr width + parameter ADDR_WIDTH=32, + //user width + parameter USER_WIDTH=4 ) + + ( + input aclk, + input aresetn, + //=========================================== + //==slave port + //=========================================== + + input [AWID_WIDTH-1:0] awid_s, + input [ADDR_WIDTH-1:0] awaddr_s, + input [7:0] awlen_s, + input [2:0] awsize_s, + input [1:0] awburst_s, + input [1:0] awlock_s, + input [3:0] awcache_s, + input [2:0] awprot_s, + input awvalid_s, + output reg awready_s, + input [USER_WIDTH-1:0] awuser_s, + input [3:0] awregion_s, + + input [AWID_WIDTH-1:0] wid_s, + input [255:0] wdata_s, + input [31:0] wstrb_s, + input wlast_s, + input wvalid_s, + output wready_s, + input [USER_WIDTH-1:0] wuser_s, + + + output reg [AWID_WIDTH-1:0] bid_s, + output reg [1:0] bresp_s, + output reg bvalid_s, + input bready_s, + output reg [USER_WIDTH-1:0] buser_s, + + + input [ARID_WIDTH-1:0] arid_s, + input [ADDR_WIDTH-1:0] araddr_s, + input [7:0] arlen_s, + input [2:0] arsize_s, + input [1:0] arburst_s, + input [1:0] arlock_s, + input [3:0] arcache_s, + input [2:0] arprot_s, + input arvalid_s, + output reg arready_s, + input [USER_WIDTH-1:0] aruser_s, + input [3:0] arregion_s, + + + output reg [ARID_WIDTH-1:0] rid_s, + output [31:0] rdata_s, + output [1:0] rresp_s, + output reg rlast_s, + output rvalid_s, + input rready_s, + output reg [USER_WIDTH-1:0] ruser_s, + + + input [3:0] awqos_s, + input [3:0] arqos_s, + + //=========================================== + //==master port + //=========================================== + output reg awvalid_m, + input awready_m, + output reg [ADDR_WIDTH-1:0] awaddr_m, + output reg [2:0] awprot_m, + output reg [USER_WIDTH-1:0] awuser_m, + + output wvalid_m, + input wready_m, + output [255:0] wdata_m, + output [31:0] wstrb_m, + + input bvalid_m, + output bready_m, + input [1:0] bresp_m, + + output reg arvalid_m, + input arready_m, + output reg [ADDR_WIDTH-1:0] araddr_m, + output reg [2:0] arprot_m, + output reg [USER_WIDTH-1:0] aruser_m, + + input rvalid_m, + output rready_m, + input [31:0] rdata_m, + input [1:0] rresp_m + ); + +localparam R_SLICE_TYPE_S=2'h0; +localparam W_SLICE_TYPE_S=2'h0; +localparam R_DATA_WIDTH_S=(32+2); +localparam W_DATA_WIDTH_S=(256+32); + +//=========================================== +//==wire and reg declaration +//=========================================== + +wire [W_DATA_WIDTH_S-1:0] src_data_w_sm , dst_data_w_sm; +wire [R_DATA_WIDTH_S-1:0] src_data_r_ms , dst_data_r_ms; +wire wready_s_l,rvalid_s_l; +wire [1:0] rresp_s_l; +wire [31:0] rdata_s_l; +wire illegal_w,illegal_r; +reg illegal_wr,illegal_rr; +reg [7:0] awlen_s_r,arlen_s_r,awaddr_cnt,araddr_cnt,bresp_cnt,rdata_cnt; +reg [1:0] awburst_s_r,arburst_s_r; +reg now_in_wr; +reg [1:0] bresp_m_r; + +//=========================================== +// -------------------------------------------------------------------- +// invalid cmd from SI will be block: +// 1. data_width != 256 +//non-bufferable not merge +//assign illegal_w = ((awsize_s != 3'b101)&&awvalid_s&&awready_s)?1'b1:1'b0; +assign illegal_w = 1'b0; +assign illegal_r = ((arsize_s != 3'b101)&&arvalid_s&&arready_s)?1'b1:1'b0; + + +always@(posedge aclk or negedge aresetn) + begin + if(~aresetn) + illegal_wr <= 1'b0; + else if(wlast_s&&wvalid_s&&wready_s) + illegal_wr <= 1'b0; + else if(illegal_w) + illegal_wr <= 1'b1; + end + +always@(posedge aclk or negedge aresetn) + begin + if(~aresetn) + illegal_rr <= 1'b0; + else if(rlast_s&&rvalid_s&&rready_s) + illegal_rr <= 1'b0; + else if(illegal_r) + illegal_rr <= 1'b1; + end + +assign wready_s = illegal_wr || (wready_s_l&&now_in_wr) ; //always wready_s when illegal +assign rvalid_s = illegal_rr || rvalid_s_l ; //always vvalid_s when illegal +assign rresp_s = illegal_rr ? 2'b10 : rresp_s_l ; //ERROR when illegal wr +assign rdata_s = illegal_rr ? 32'h0 : rdata_s_l ; //read data all-0 when illegal rd + + +//=========================================== +// aw channel +//=========================================== + +//axi-port +always@(posedge aclk or negedge aresetn) + begin + if(~aresetn) + awready_s <= 1'b1; + else if(bvalid_s&&bready_s) + awready_s <= 1'b1; + else if(awvalid_s&&awready_s) + awready_s <= 1'b0; + end + +//axilite-port +always@(posedge aclk or negedge aresetn) + begin + if(~aresetn) + awvalid_m <= 1'b0; + else if(awvalid_s&&awready_s&&(~illegal_w)) + awvalid_m <= 1'b1; + else if(awvalid_m&&awready_m&&((awaddr_cnt==awlen_s_r))) + awvalid_m <= 1'b0; + end + +always@(posedge aclk or negedge aresetn) + begin + if(~aresetn) + awaddr_m <= {ADDR_WIDTH{1'b0}}; + else if(awvalid_s&&awready_s&&(~illegal_w)) + awaddr_m <= {awaddr_s[ADDR_WIDTH-1:5],5'b00};//address not change in 32B + else if(awvalid_m&&awready_m&&(awaddr_cnt!=awlen_s_r)) + begin + if(awburst_s_r==2'b01)//INCR: Updated + awaddr_m <= awaddr_m + {{(ADDR_WIDTH-4){1'b0}},4'd8}; + else if(awburst_s_r == 2'b10)//WRAP: dont touched + begin + if(awlen_s_r[7]) + awaddr_m <= {awaddr_m[ADDR_WIDTH-1:10],(awaddr_m[9:0] + 10'h4)}; + else if(awlen_s_r[6]) + awaddr_m <= {awaddr_m[ADDR_WIDTH-1:9],(awaddr_m[8:0] + 9'h4)}; + else if(awlen_s_r[5]) + awaddr_m <= {awaddr_m[ADDR_WIDTH-1:8],(awaddr_m[7:0] + 8'h4)}; + else if(awlen_s_r[4]) + awaddr_m <= {awaddr_m[ADDR_WIDTH-1:7],(awaddr_m[6:0] + 7'h4)}; + else if(awlen_s_r[3]) + awaddr_m <= {awaddr_m[ADDR_WIDTH-1:6],(awaddr_m[5:0] + 6'h4)}; + else if(awlen_s_r[2]) + awaddr_m <= {awaddr_m[ADDR_WIDTH-1:5],(awaddr_m[4:0] + 5'h4)}; + else if(awlen_s_r[1]) + awaddr_m <= {awaddr_m[ADDR_WIDTH-1:4],(awaddr_m[3:0] + 4'h4)}; + else if(awlen_s_r[0]) + awaddr_m <= {awaddr_m[ADDR_WIDTH-1:3],(awaddr_m[2:0] + 3'h4)}; + end + end + end + + +always@(posedge aclk or negedge aresetn) + begin + if(~aresetn) + begin + awprot_m <= 3'h0; + awuser_m <= {USER_WIDTH{1'b0}}; + end + else if(awvalid_s&&awready_s) + begin + awprot_m <= awprot_s; + awuser_m <= awuser_s; + end + end + +//local signal +always@(posedge aclk or negedge aresetn) + begin + if(~aresetn) + awaddr_cnt <= 8'h0; + else if(awvalid_s&&awready_s) + awaddr_cnt <= 8'h0; + else if(awvalid_m&&awready_m&&(awaddr_cnt!=awlen_s_r)) + awaddr_cnt <= awaddr_cnt + 8'h1; + end + +always@(posedge aclk or negedge aresetn) + begin + if(~aresetn) + begin + awlen_s_r <= 8'h0; + awburst_s_r <= 2'h0; + end + else if(awvalid_s&&awready_s) + begin + awlen_s_r <= awlen_s; + awburst_s_r <= awburst_s; + end + end + + + +//=========================================== +// wdata channel +//=========================================== + +assign src_data_w_sm={ +wstrb_s, +wdata_s +}; +assign { +wstrb_m, +wdata_m +}=dst_data_w_sm; +axi_slice #( + .HNDSHK_MODE(W_SLICE_TYPE_S), + .PAYLD_WIDTH(W_DATA_WIDTH_S)) + u_axi_w_sm( + // Outputs + .dst_data (dst_data_w_sm), // Templated + .src_ready (wready_s_l), // Templated + .dst_valid (wvalid_m), // Templated + // Inputs + .aresetn (aresetn), + .aclk (aclk), + .src_data (src_data_w_sm), // Templated + .src_valid (wvalid_s&&(~illegal_wr)&&now_in_wr), // Templated + .dst_ready (wready_m)); // Templated + + +always@(posedge aclk or negedge aresetn) + begin + if(~aresetn) + now_in_wr <= 1'b0; + else if(wlast_s&&wvalid_s&&wready_s) + now_in_wr <= 1'b0; + else if(awvalid_s&&awready_s) + now_in_wr <= 1'b1; + end + +//=========================================== +//b channel +//=========================================== + +//axi-port +always@(posedge aclk or negedge aresetn) + begin + if(~aresetn) + bresp_s <= 2'h0; + else if(bvalid_s&&bready_s) + bresp_s <= 2'h0; + else if((bresp_cnt == awlen_s_r)&&illegal_wr&&wvalid_s&&wready_s) + bresp_s <= 2'b10; + else if((bresp_cnt == awlen_s_r)&&bvalid_m&&bready_m) + begin + if(bresp_m_r != 2'h0) + bresp_s <= bresp_m_r; + else + bresp_s <= bresp_m; + end + end + + +always@(posedge aclk or negedge aresetn) + begin + if(~aresetn) + bresp_m_r <= 2'h0; + else if(bvalid_s&&bready_s) + bresp_m_r <= 2'h0; + else if((bresp_m_r == 2'h0)&&(bresp_m != 2'h0)&&bvalid_m&&bready_m)//store 1st ERROR + bresp_m_r <= bresp_m; + end + +always@(posedge aclk or negedge aresetn) + begin + if(~aresetn) + bvalid_s <= 1'b0; + else if(bvalid_s&&bready_s) + bvalid_s <= 1'b0; + else if(wlast_s&&wvalid_s&&wready_s&&illegal_wr)//illegal bresp + bvalid_s <= 1'b1; + else if((bresp_cnt == awlen_s_r)&&bvalid_m&&bready_m) + bvalid_s <= 1'b1; + end + +always @(posedge aclk or negedge aresetn) + begin + if(~aresetn) + bid_s <= {ARID_WIDTH{1'b0}}; + else if(awvalid_s&&awready_s) + bid_s <= awid_s; + end + +always@(posedge aclk or negedge aresetn) + begin + if(~aresetn) + buser_s <= {USER_WIDTH{1'b0}}; + else if(awvalid_s&&awready_s) + buser_s <= awuser_s; + end + +//axilite-port +assign bready_m = 1'b1; + +//local signals +always@(posedge aclk or negedge aresetn) + begin + if(~aresetn) + bresp_cnt <= 8'h0; + else if(bvalid_s&&bready_s) + bresp_cnt <= 8'h0; + else if(illegal_wr&&wvalid_s&&wready_s) + bresp_cnt <= bresp_cnt + 8'h1; + else if(bvalid_m&&bready_m) + bresp_cnt <= bresp_cnt + 8'h1; + end + +//=========================================== +// ar channel +//=========================================== + +//axi-port +always@(posedge aclk or negedge aresetn) + begin + if(~aresetn) + arready_s <= 1'b1; + else if(rvalid_s&&rready_s&&rlast_s) + arready_s <= 1'b1; + else if(arvalid_s&&arready_s) + arready_s <= 1'b0; + end + +//axilite-port + +always@(posedge aclk or negedge aresetn) + begin + if(~aresetn) + arvalid_m <= 1'b0; + else if(arvalid_s&&arready_s&&(~illegal_r)) + arvalid_m <= 1'b1; + else if(arvalid_m&&arready_m&&((araddr_cnt==arlen_s_r))) + arvalid_m <= 1'b0; + end + +always@(posedge aclk or negedge aresetn) + begin + if(~aresetn) + araddr_m <= {ADDR_WIDTH{1'b0}}; + else if(arvalid_s&&arready_s&&(~illegal_r)) + araddr_m <= {araddr_s[ADDR_WIDTH-1:2],2'b00}; //if unalign + else if(arvalid_m&&arready_m&&(araddr_cnt!=arlen_s_r)) + begin + if(arburst_s_r==2'b01)//INCR + araddr_m <= araddr_m + {{(ADDR_WIDTH-3){1'b0}},3'h4}; + else if(arburst_s_r == 2'b10)//WRAP + begin + if(arlen_s_r[7]) + araddr_m <= {araddr_m[ADDR_WIDTH-1:10],(araddr_m[9:0] + 10'h4)}; + else if(arlen_s_r[6]) + araddr_m <= {araddr_m[ADDR_WIDTH-1:9],(araddr_m[8:0] + 9'h4)}; + else if(arlen_s_r[5]) + araddr_m <= {araddr_m[ADDR_WIDTH-1:8],(araddr_m[7:0] + 8'h4)}; + else if(arlen_s_r[4]) + araddr_m <= {araddr_m[ADDR_WIDTH-1:7],(araddr_m[6:0] + 7'h4)}; + else if(arlen_s_r[3]) + araddr_m <= {araddr_m[ADDR_WIDTH-1:6],(araddr_m[5:0] + 6'h4)}; + else if(arlen_s_r[2]) + araddr_m <= {araddr_m[ADDR_WIDTH-1:5],(araddr_m[4:0] + 5'h4)}; + else if(arlen_s_r[1]) + araddr_m <= {araddr_m[ADDR_WIDTH-1:4],(araddr_m[3:0] + 4'h4)}; + else if(arlen_s_r[0]) + araddr_m <= {araddr_m[ADDR_WIDTH-1:3],(araddr_m[2:0] + 3'h4)}; + end + end + end + + +always@(posedge aclk or negedge aresetn) + begin + if(~aresetn) + begin + arprot_m <= 3'h0; + aruser_m <= {USER_WIDTH{1'b0}}; + end + else if(arvalid_s&&arready_s&&(~illegal_r)) + begin + arprot_m <= arprot_s; + aruser_m <= aruser_s; + end + end + +//local signals +always@(posedge aclk or negedge aresetn) + begin + if(~aresetn) + begin + araddr_cnt <= 8'h0; + arlen_s_r <= 8'h0; + arburst_s_r <= 2'h0; + end + else if(arvalid_s&&arready_s) + begin + araddr_cnt <= 8'h0; + arlen_s_r <= arlen_s; + arburst_s_r <= arburst_s; + end + else if(arvalid_m&&arready_m&&(araddr_cnt!=arlen_s_r)) + araddr_cnt <= araddr_cnt + 8'h1; + end + + +//=========================================== +// rdata channel +//=========================================== + +assign src_data_r_ms={ +rresp_m, +rdata_m +}; +assign { +rresp_s_l, +rdata_s_l +}=dst_data_r_ms; +axi_slice #( + .HNDSHK_MODE(R_SLICE_TYPE_S), + .PAYLD_WIDTH(R_DATA_WIDTH_S)) + u_axi_r_ms( + // Outputs + .dst_data (dst_data_r_ms), // Templated + .src_ready (rready_m), // Templated + .dst_valid (rvalid_s_l), // Templated + // Inputs + .aresetn (aresetn), + .aclk (aclk), + .src_data (src_data_r_ms), // Templated + .src_valid (rvalid_m), // Templated + .dst_ready (rready_s)); // Templated + +//axi-port +always @(posedge aclk or negedge aresetn) + begin + if(~aresetn) + begin + rid_s <= {ARID_WIDTH{1'b0}}; + ruser_s <= {USER_WIDTH{1'b0}}; + end + else if(arvalid_s&&arready_s) + begin + rid_s <= arid_s; + ruser_s <= aruser_s; + end + end + + +//local signals +always @(posedge aclk or negedge aresetn) + begin + if(~aresetn) + rdata_cnt <= 8'h0; + else if(rlast_s) + rdata_cnt <= 8'h0; + else if(rvalid_s&&rready_s) + rdata_cnt <= rdata_cnt + 8'h1; + end + +always@(posedge aclk or negedge aresetn) + begin + if(~aresetn) + rlast_s <= 1'b0; + else if(rlast_s&&rvalid_s&&rready_s) + rlast_s <= 1'b0; + else if((arlen_s == 8'h0)&&arvalid_s&&arready_s) + rlast_s <= 1'b1; + else if((rdata_cnt == (arlen_s_r - 8'h1))&&rvalid_s&&rready_s) + rlast_s <= 1'b1; + end + +endmodule
diff --git a/axi2sramcrs/rtl/axi2sramcrs.v b/axi2sramcrs/rtl/axi2sramcrs.v new file mode 100644 index 0000000..216c01a --- /dev/null +++ b/axi2sramcrs/rtl/axi2sramcrs.v
@@ -0,0 +1,347 @@ +//**************************************************************************** +// +// Copyright 2017-2023 Vivante Corporation +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +//**************************************************************************** +// Auto-generated file on 11/03/2023. +// +//**************************************************************************** + +module axi2sramcrs #( + parameter ARID_WIDTH=4, + parameter AWID_WIDTH=4, + parameter ADDR_WIDTH=32, + parameter US_DATA_WIDTH=64, + parameter DS_DATA_WIDTH=256, + parameter USER_WIDTH=16, + parameter IS_AXI3=1'h1, + parameter AXLEN_WIDTH=(IS_AXI3==1'h1) ? 4 : 8, + parameter RD_ISS=128, + parameter WR_ISS=128, + parameter DS_WSTRB_WIDTH=DS_DATA_WIDTH/8, + parameter US_WSTRB_WIDTH=US_DATA_WIDTH/8) +( + input aclk, + input aresetn, + + input [AWID_WIDTH-1:0] awid_s, + input [ADDR_WIDTH-1:0] awaddr_s, + input [AXLEN_WIDTH-1:0] awlen_s, + input [2:0] awsize_s, + input [1:0] awburst_s, + input [1:0] awlock_s, + input [3:0] awcache_s, + input [2:0] awprot_s, + input awvalid_s, + output awready_s, + input [USER_WIDTH-1:0] awuser_s, + input [3:0] awregion_s, + input [US_DATA_WIDTH-1:0] wdata_s, + input [US_WSTRB_WIDTH-1:0] wstrb_s, + input wlast_s, + input wvalid_s, + output wready_s, + input [AWID_WIDTH-1:0] wid_s, + input [USER_WIDTH-1:0] wuser_s, + output [AWID_WIDTH-1:0] bid_s, + output [1:0] bresp_s, + output bvalid_s, + input bready_s, + output [USER_WIDTH-1:0] buser_s, + input [3:0] awqos_s, + + output sram_cvalid, + input sram_cready, + output sram_cwrite, + output [31:0] sram_caddr, + output [7:0] sram_cid, + output [255:0] sram_wdata, + output [31:0] sram_wmask +); + +localparam DS_AXI3=IS_AXI3; +localparam DS_ADDR_AL_WIDTH=$clog2(DS_WSTRB_WIDTH); +localparam US_ADDR_AL_WIDTH=$clog2(US_WSTRB_WIDTH); +localparam ARFMT_WIDTH=1+1+ARID_WIDTH+DS_ADDR_AL_WIDTH*3+1+3; +localparam AWFMT_WIDTH=AWID_WIDTH+1+4+1+DS_ADDR_AL_WIDTH*2+3+1; +localparam US_AW_WIDTH=4+USER_WIDTH+AWID_WIDTH+ADDR_WIDTH+8+3+2+2+4+4+3+1; +localparam US_AR_WIDTH=4+USER_WIDTH+ARID_WIDTH+ADDR_WIDTH+8+3+2+2+4+4+3+1; +localparam US_R_WIDTH=USER_WIDTH+ARID_WIDTH+US_DATA_WIDTH+2+1; +localparam US_W_WIDTH=USER_WIDTH+AWID_WIDTH+US_DATA_WIDTH+US_WSTRB_WIDTH+1; +localparam US_B_WIDTH=USER_WIDTH+AWID_WIDTH+2; +localparam AW_IDB_WIDTH=US_AW_WIDTH; +localparam AR_IDB_WIDTH=US_AR_WIDTH; +localparam W_IDB_WIDTH=AWID_WIDTH+USER_WIDTH+DS_DATA_WIDTH+DS_WSTRB_WIDTH+1; +localparam R_IDB_WIDTH=USER_WIDTH+ARID_WIDTH+DS_DATA_WIDTH+2+1; +localparam B_IDB_WIDTH=USER_WIDTH+2+AWID_WIDTH; + + +//Interface between upsizer and axi2axilite +wire [AWID_WIDTH-1:0] awid_m; +wire [ADDR_WIDTH-1:0] awaddr_m; +wire [AXLEN_WIDTH-1:0] awlen_m; +wire [2:0] awsize_m; +wire [1:0] awburst_m; +wire [1:0] awlock_m; +wire [3:0] awcache_m; +wire [2:0] awprot_m; +wire awvalid_m; +wire awready_m; +wire [USER_WIDTH-1:0] awuser_m; +wire [3:0] awregion_m; +wire [DS_DATA_WIDTH-1:0] wdata_m; +wire [DS_WSTRB_WIDTH-1:0] wstrb_m; +wire wlast_m; +wire wvalid_m; +wire wready_m; +wire [AWID_WIDTH-1:0] wid_m; +wire [USER_WIDTH-1:0] wuser_m; +wire [AWID_WIDTH-1:0] bid_m; +wire [1:0] bresp_m; +wire bvalid_m; +wire bready_m; +wire [USER_WIDTH-1:0] buser_m; +wire [ARID_WIDTH-1:0] arid_m; +wire [ADDR_WIDTH-1:0] araddr_m; +wire [AXLEN_WIDTH-1:0] arlen_m; +wire [2:0] arsize_m; +wire [1:0] arburst_m; +wire [1:0] arlock_m; +wire [3:0] arcache_m; +wire [2:0] arprot_m; +wire arvalid_m; +wire arready_m; +wire [USER_WIDTH-1:0] aruser_m; +wire [3:0] arregion_m; +wire [ARID_WIDTH-1:0] rid_m; +wire [DS_DATA_WIDTH-1:0] rdata_m; +wire [1:0] rresp_m; +wire rlast_m; +wire rvalid_m; +wire rready_m; +wire [USER_WIDTH-1:0] ruser_m; +wire [3:0] awqos_m; +wire [3:0] arqos_m; +//Interface between axi2axilite and axilite2sram +wire awvalid_lite_m; +wire awready_lite_m; +wire [ADDR_WIDTH-1:0] awaddr_lite_m; +wire [2:0] awprot_lite_m; +wire [USER_WIDTH-1:0] awuser_lite_m; +wire wvalid_lite_m; +wire wready_lite_m; +wire [255:0] wdata_lite_m; +wire [31:0] wstrb_lite_m; +wire bvalid_lite_m; +wire bready_lite_m; +wire [1:0] bresp_lite_m; + +axi_upsizer u_upsizer(/*AUTOINST*/ + // Outputs + .awid_m (awid_m[AWID_WIDTH-1:0]), + .awaddr_m (awaddr_m[ADDR_WIDTH-1:0]), + .awlen_m (awlen_m[AXLEN_WIDTH-1:0]), + .awsize_m (awsize_m[2:0]), + .awburst_m (awburst_m[1:0]), + .awlock_m (awlock_m[1:0]), + .awcache_m (awcache_m[3:0]), + .awprot_m (awprot_m[2:0]), + .awvalid_m (awvalid_m), + .awuser_m (awuser_m[USER_WIDTH-1:0]), + .awregion_m (awregion_m[3:0]), + .wdata_m (wdata_m[DS_DATA_WIDTH-1:0]), + .wstrb_m (wstrb_m[DS_WSTRB_WIDTH-1:0]), + .wlast_m (wlast_m), + .wvalid_m (wvalid_m), + .wid_m (wid_m[AWID_WIDTH-1:0]), + .wuser_m (wuser_m[USER_WIDTH-1:0]), + .bready_m (bready_m), + .arid_m (arid_m[ARID_WIDTH-1:0]), + .araddr_m (araddr_m[ADDR_WIDTH-1:0]), + .arlen_m (arlen_m[AXLEN_WIDTH-1:0]), + .arsize_m (arsize_m[2:0]), + .arburst_m (arburst_m[1:0]), + .arlock_m (arlock_m[1:0]), + .arcache_m (arcache_m[3:0]), + .arprot_m (arprot_m[2:0]), + .arvalid_m (arvalid_m), + .aruser_m (aruser_m[USER_WIDTH-1:0]), + .arregion_m (arregion_m[3:0]), + .rready_m (rready_m), + .awqos_m (awqos_m[3:0]), + .arqos_m (arqos_m[3:0]), + .awready_s (awready_s), + .wready_s (wready_s), + .bid_s (bid_s[AWID_WIDTH-1:0]), + .bresp_s (bresp_s[1:0]), + .bvalid_s (bvalid_s), + .buser_s (buser_s[USER_WIDTH-1:0]), + .arready_s (), + .rid_s (), + .rdata_s (), + .rresp_s (), + .rlast_s (), + .rvalid_s (), + .ruser_s (), + // Inputs + .aclk (aclk), + .aresetn (aresetn), + .awready_m (awready_m), + .wready_m (wready_m), + .bid_m (bid_m[AWID_WIDTH-1:0]), + .bresp_m (bresp_m[1:0]), + .bvalid_m (bvalid_m), + .buser_m (buser_m[USER_WIDTH-1:0]), + .arready_m (arready_m), + .rid_m (rid_m[ARID_WIDTH-1:0]), + .rdata_m (rdata_m[DS_DATA_WIDTH-1:0]), + .rresp_m (rresp_m[1:0]), + .rlast_m (rlast_m), + .rvalid_m (rvalid_m), + .ruser_m (ruser_m[USER_WIDTH-1:0]), + .awid_s (awid_s[AWID_WIDTH-1:0]), + .awaddr_s (awaddr_s[ADDR_WIDTH-1:0]), + .awlen_s (awlen_s[AXLEN_WIDTH-1:0]), + .awsize_s (awsize_s[2:0]), + .awburst_s (awburst_s[1:0]), + .awlock_s (awlock_s[1:0]), + .awcache_s (awcache_s[3:0]), + .awprot_s (awprot_s[2:0]), + .awvalid_s (awvalid_s), + .awuser_s (awuser_s[USER_WIDTH-1:0]), + .awregion_s (awregion_s[3:0]), + .wdata_s (wdata_s[US_DATA_WIDTH-1:0]), + .wstrb_s (wstrb_s[US_WSTRB_WIDTH-1:0]), + .wlast_s (wlast_s), + .wvalid_s (wvalid_s), + .wid_s (wid_s[AWID_WIDTH-1:0]), + .wuser_s (wuser_s[USER_WIDTH-1:0]), + .bready_s (bready_s), + .arid_s (4'b0), + .araddr_s (32'b0), + .arlen_s (4'b0), + .arsize_s (3'b0), + .arburst_s (2'b0), + .arlock_s (2'b0), + .arcache_s (4'b0), + .arprot_s (3'b0), + .arvalid_s (1'b0), + .aruser_s (16'b0), + .arregion_s (4'b0), + .rready_s (1'b0), + .awqos_s (awqos_m[3:0]), + .arqos_s (4'b0)); + + +axi2axilite u_axi2axilite(/*AUTOINST*/ + // Outputs + .awready_s (awready_m), + .wready_s (wready_m), + .bid_s (bid_m[AWID_WIDTH-1:0]), + .bresp_s (bresp_m[1:0]), + .bvalid_s (bvalid_m), + .buser_s (buser_m[USER_WIDTH-1:0]), + .arready_s (arready_m), + .rid_s (rid_m[ARID_WIDTH-1:0]), + .rdata_s (rdata_m[31:0]), + .rresp_s (rresp_m[1:0]), + .rlast_s (rlast_m), + .rvalid_s (rvalid_m), + .ruser_s (ruser_m[USER_WIDTH-1:0]), + .awvalid_m (awvalid_lite_m), + .awaddr_m (awaddr_lite_m[ADDR_WIDTH-1:0]), + .awprot_m (awprot_lite_m[2:0]), + .awuser_m (awuser_lite_m[USER_WIDTH-1:0]), + .wvalid_m (wvalid_lite_m), + .wdata_m (wdata_lite_m[255:0]), + .wstrb_m (wstrb_lite_m[31:0]), + .bready_m (bready_lite_m), + .arvalid_m (),//Floating + .araddr_m (),//Floating + .arprot_m (),//Floating + .aruser_m (),//Floating + .rready_m (),//Floating + // Inputs + .aclk (aclk), + .aresetn (aresetn), + .awid_s (awid_m[AWID_WIDTH-1:0]), + .awaddr_s (awaddr_m[ADDR_WIDTH-1:0]), + .awlen_s ({4'b0,awlen_m[3:0]}), + .awsize_s (awsize_m[2:0]), + .awburst_s (awburst_m[1:0]), + .awlock_s (awlock_m[1:0]), + .awcache_s (awcache_m[3:0]), + .awprot_s (awprot_m[2:0]), + .awvalid_s (awvalid_m), + .awuser_s (awuser_m[USER_WIDTH-1:0]), + .awregion_s (awregion_m[3:0]), + .wid_s (wid_m[AWID_WIDTH-1:0]), + .wdata_s (wdata_m[255:0]), + .wstrb_s (wstrb_m[31:0]), + .wlast_s (wlast_m), + .wvalid_s (wvalid_m), + .wuser_s (wuser_m[USER_WIDTH-1:0]), + .bready_s (bready_m), + .arid_s (arid_m[ARID_WIDTH-1:0]), + .araddr_s (araddr_m[ADDR_WIDTH-1:0]), + .arlen_s ({4'b0,arlen_m[3:0]}), + .arsize_s (arsize_m[2:0]), + .arburst_s (arburst_m[1:0]), + .arlock_s (arlock_m[1:0]), + .arcache_s (arcache_m[3:0]), + .arprot_s (arprot_m[2:0]), + .arvalid_s (arvalid_m), + .aruser_s (aruser_m[USER_WIDTH-1:0]), + .arregion_s (arregion_m[3:0]), + .rready_s (rready_m), + .awqos_s (awqos_m[3:0]), + .arqos_s (arqos_m[3:0]), + .awready_m (awready_lite_m), + .wready_m (wready_lite_m), + .bvalid_m (bvalid_lite_m), + .bresp_m (bresp_lite_m[1:0]), + .arready_m (1'b0),//Tie + .rvalid_m (1'b0),//Tie + .rdata_m (32'b0),//Tie + .rresp_m (2'b0));//Tie + +axilite2sram u_axilite2sram(/*AUTOINST*/ + // Outputs + .awready_s (awready_lite_m), + .wready_s (wready_lite_m), + .bvalid_s (bvalid_lite_m), + .bresp_s (bresp_lite_m[1:0]), + .sram_cvalid (sram_cvalid), + .sram_cwrite (sram_cwrite), + .sram_caddr (sram_caddr[31:0]), + .sram_cid (sram_cid[7:0]), + .sram_wdata (sram_wdata[255:0]), + .sram_wmask (sram_wmask[31:0]), + // Inputs + .aclk (aclk), + .aresetn (aresetn), + .awvalid_s (awvalid_lite_m), + .awaddr_s (awaddr_lite_m[ADDR_WIDTH-1:0]), + .awprot_s (awprot_lite_m[2:0]), + .awuser_s (awuser_lite_m[USER_WIDTH-1:0]), + .wvalid_s (wvalid_lite_m), + .wdata_s (wdata_lite_m[255:0]), + .wstrb_s (wstrb_lite_m[31:0]), + .bready_s (bready_lite_m), + .sram_cready (sram_cready)); + + + +endmodule
diff --git a/axi2sramcrs/rtl/axilite2sram.v b/axi2sramcrs/rtl/axilite2sram.v new file mode 100644 index 0000000..1c95d24 --- /dev/null +++ b/axi2sramcrs/rtl/axilite2sram.v
@@ -0,0 +1,113 @@ +//**************************************************************************** +// +// Copyright 2017-2023 Vivante Corporation +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +//**************************************************************************** +// Auto-generated file on 11/03/2023. +// +//**************************************************************************** + +module axilite2sram + #( + //id width + parameter ARID_WIDTH=4, + parameter AWID_WIDTH=4, + //addr width + parameter ADDR_WIDTH=32, + //user width + parameter USER_WIDTH=4 ) + +( + input aclk, + input aresetn, + //=========================================== + //==slave port write only + //=========================================== + input awvalid_s, + output awready_s, + input [ADDR_WIDTH-1:0] awaddr_s, + input [2:0] awprot_s,//N.A + input [USER_WIDTH-1:0] awuser_s,//N.A + + input wvalid_s, + output wready_s, + input [255:0] wdata_s, + input [31:0] wstrb_s, + + output reg bvalid_s, + input bready_s, + output [1:0] bresp_s, + + output sram_cvalid, + input sram_cready, + output sram_cwrite, + output [31:0] sram_caddr, + output [7:0] sram_cid, + output [255:0] sram_wdata, + output [31:0] sram_wmask +); + + +reg awvalid_latch; +reg [31:0] awaddr_latch; + +assign wready_s = awvalid_latch & sram_cready; +//assign awready_s = awvalid_latch1'b1; +assign awready_s = ~awvalid_latch;//no more ostd +assign bresp_s = 2'b0; + +assign sram_wdata = wdata_s; +assign sram_wmask = wstrb_s; +assign sram_cid = 8'b0; + +always@(posedge aclk or negedge aresetn) + begin + if(~aresetn) + awvalid_latch <= 1'b0; + else if(awvalid_s&&awready_s) + awvalid_latch <= 1'b1; +// else if(bvalid_s&&bready_s) +// awvalid_latch <= 1'b0; + else if(wvalid_s&&wready_s) + awvalid_latch <= 1'b0; + end + +always@(posedge aclk or negedge aresetn) + begin + if(~aresetn) + awaddr_latch <= 32'b0; + else if(awvalid_s&&awready_s) + awaddr_latch <= awaddr_s; + end + +always@(posedge aclk or negedge aresetn) + begin + if(~aresetn) + bvalid_s <= 1'b0; + else if(bvalid_s&bready_s) + bvalid_s <= 1'b0; + else if(wvalid_s&&wready_s) + bvalid_s <= 1'b1; + end + + +assign sram_cvalid = awvalid_latch && wvalid_s; +//assign sram_cvalid = wvalid_s; +assign sram_cwrite = awvalid_latch && wvalid_s; +//assign sram_cwrite = wvalid_s; +assign sram_caddr = awaddr_latch; + + +endmodule
diff --git a/axi2sramcrs/rtl/share/Axi.v b/axi2sramcrs/rtl/share/Axi.v new file mode 100644 index 0000000..45cf494 --- /dev/null +++ b/axi2sramcrs/rtl/share/Axi.v
@@ -0,0 +1,55 @@ +//**************************************************************************** +// +// Copyright 2017-2023 Vivante Corporation +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +//**************************************************************************** +// Auto-generated file on 11/03/2023. +// +//**************************************************************************** + +`define AXI_ALEN_1 4'b0000 +`define AXI_ALEN_2 4'b0001 +`define AXI_ALEN_3 4'b0010 +`define AXI_ALEN_4 4'b0011 +`define AXI_ALEN_5 4'b0100 +`define AXI_ALEN_6 4'b0101 +`define AXI_ALEN_7 4'b0110 +`define AXI_ALEN_8 4'b0111 +`define AXI_ALEN_9 4'b1000 +`define AXI_ALEN_10 4'b1001 +`define AXI_ALEN_11 4'b1010 +`define AXI_ALEN_12 4'b1011 +`define AXI_ALEN_13 4'b1100 +`define AXI_ALEN_14 4'b1101 +`define AXI_ALEN_15 4'b1110 +`define AXI_ALEN_16 4'b1111 +`define AXI_ASIZE_8 3'b000 +`define AXI_ASIZE_16 3'b001 +`define AXI_ASIZE_32 3'b010 +`define AXI_ASIZE_64 3'b011 +`define AXI_ASIZE_128 3'b100 +`define AXI_ASIZE_256 3'b101 +`define AXI_ASIZE_512 3'b110 +`define AXI_ASIZE_1024 3'b111 +`define AXI_ABURST_FIXED 2'b00 +`define AXI_ABURST_INCR 2'b01 +`define AXI_ABURST_WRAP 2'b10 +`define AXI_ALOCK_NOLOCK 2'b00 +`define AXI_ALOCK_EXCL 2'b01 +`define AXI_ALOCK_LOCKED 2'b10 +`define AXI_RESP_OKAY 2'b00 +`define AXI_RESP_EXOKAY 2'b01 +`define AXI_RESP_SLVERR 2'b10 +`define AXI_RESP_DECERR 2'b11
diff --git a/axi2sramcrs/rtl/share/Axi_undefs.v b/axi2sramcrs/rtl/share/Axi_undefs.v new file mode 100644 index 0000000..0854a76 --- /dev/null +++ b/axi2sramcrs/rtl/share/Axi_undefs.v
@@ -0,0 +1,55 @@ +//**************************************************************************** +// +// Copyright 2017-2023 Vivante Corporation +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +//**************************************************************************** +// Auto-generated file on 11/03/2023. +// +//**************************************************************************** + +`undef AXI_ALEN_1 +`undef AXI_ALEN_2 +`undef AXI_ALEN_3 +`undef AXI_ALEN_4 +`undef AXI_ALEN_5 +`undef AXI_ALEN_6 +`undef AXI_ALEN_7 +`undef AXI_ALEN_8 +`undef AXI_ALEN_9 +`undef AXI_ALEN_10 +`undef AXI_ALEN_11 +`undef AXI_ALEN_12 +`undef AXI_ALEN_13 +`undef AXI_ALEN_14 +`undef AXI_ALEN_15 +`undef AXI_ALEN_16 +`undef AXI_ASIZE_8 +`undef AXI_ASIZE_16 +`undef AXI_ASIZE_32 +`undef AXI_ASIZE_64 +`undef AXI_ASIZE_128 +`undef AXI_ASIZE_256 +`undef AXI_ASIZE_512 +`undef AXI_ASIZE_1024 +`undef AXI_ABURST_FIXED +`undef AXI_ABURST_INCR +`undef AXI_ABURST_WRAP +`undef AXI_ALOCK_NOLOCK +`undef AXI_ALOCK_EXCL +`undef AXI_ALOCK_LOCKED +`undef AXI_RESP_OKAY +`undef AXI_RESP_EXOKAY +`undef AXI_RESP_SLVERR +`undef AXI_RESP_DECERR
diff --git a/axi2sramcrs/rtl/share/axi_slice/axi_ful_regd_slice.v b/axi2sramcrs/rtl/share/axi_slice/axi_ful_regd_slice.v new file mode 100644 index 0000000..08097bc --- /dev/null +++ b/axi2sramcrs/rtl/share/axi_slice/axi_ful_regd_slice.v
@@ -0,0 +1,144 @@ +//**************************************************************************** +// +// Copyright 2017-2023 Vivante Corporation +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +//**************************************************************************** +// Auto-generated file on 11/03/2023. +// +//**************************************************************************** + +module axi_ful_regd_slice + ( + aresetn, + aclk, + valid_src, + ready_dst, + payload_src, + valid_dst, + ready_src, + payload_dst + ); + parameter PAYLD_WIDTH = 2; + parameter PAYLD_MAX = (PAYLD_WIDTH - 1); + parameter NUM_SEL_LINES = (PAYLD_WIDTH + 7) / 8; + parameter REM_SEL_LINE = (((PAYLD_WIDTH - 1) % 8) + 1); + input aresetn; + input aclk; + input valid_src; + input ready_dst; + input [PAYLD_MAX:0] payload_src; + output valid_dst; + output ready_src; + output [PAYLD_MAX:0] payload_dst; + wire aresetn; + wire aclk; + wire valid_src; + wire ready_dst; + wire [PAYLD_MAX:0] payload_src; + wire valid_dst; + wire ready_src; + reg [PAYLD_MAX:0] payload_dst; + wire enable_a; + wire enable_b; + wire load_sel_en; + wire nxt_valid_a; + wire nxt_valid_b; + reg [PAYLD_MAX:0] payload_reg_a; + reg [PAYLD_MAX:0] payload_reg_b; + reg valid_a; + reg valid_b; + wire iready_src; + wire ivalid_dst; + reg load_b; + reg [NUM_SEL_LINES:0] sel_b; + wire sel_b_en; + assign valid_dst = ivalid_dst; + assign ready_src = iready_src; + always @(sel_b or payload_reg_a or payload_reg_b) + begin : p_payload_mux + integer i; + integer j; + integer base; + base = 0; + for (i=1; i<NUM_SEL_LINES; i=i+1) + begin + for (j=base; j<(base+8); j=j+1) + payload_dst[j] = (sel_b[i] ? payload_reg_b[j] : payload_reg_a[j]); + base = (8 * i); + end + for (j=base; j<(base+REM_SEL_LINE); j=j+1) + payload_dst[j] = (sel_b[NUM_SEL_LINES] ? payload_reg_b[j] : payload_reg_a[j]); + end + assign enable_a = ~load_b & valid_src & iready_src; + assign enable_b = load_b & valid_src & iready_src; + assign load_sel_en = valid_src & iready_src; + assign nxt_valid_a = (enable_a ? 1'b1 + :((~sel_b[0] & ivalid_dst & ready_dst) ? 1'b0 + : valid_a)); + assign nxt_valid_b = (enable_b ? 1'b1 + :((sel_b[0] & ivalid_dst & ready_dst) ? 1'b0 + : valid_b)); + //end + always @(posedge aclk or negedge aresetn) + begin : p_payload_reg_a + if (~aresetn) + payload_reg_a <= {PAYLD_WIDTH{1'b0}}; + else if (enable_a) + payload_reg_a <= payload_src; + end + //end + always @(posedge aclk or negedge aresetn) + begin : p_payload_reg_b + if (~aresetn) + payload_reg_b <= {PAYLD_WIDTH{1'b0}}; + else if (enable_b) + payload_reg_b <= payload_src; + end + always @(posedge aclk or negedge aresetn) + begin : p_valid_a + if (~aresetn) + valid_a <= 1'b0; + else + valid_a <= nxt_valid_a; + end + always @(posedge aclk or negedge aresetn) + begin : p_valid_b + if (~aresetn) + valid_b <= 1'b0; + else + valid_b <= nxt_valid_b; + end + assign iready_src = ~valid_a | ~valid_b; + assign ivalid_dst = valid_a | valid_b; + always @(posedge aclk or negedge aresetn) + begin : p_load_b + if (~aresetn) + load_b <= 1'b0; + else + if (load_sel_en) + load_b <= ~load_b; + end + assign sel_b_en = ((~sel_b[0] & nxt_valid_b & (~valid_a | ready_dst)) | + ( sel_b[0] & nxt_valid_a & (~valid_b | ready_dst))); + + always @(posedge aclk or negedge aresetn) + begin : p_sel_b + if (~aresetn) + sel_b <= {NUM_SEL_LINES+1{1'b0}}; + else + if (sel_b_en) + sel_b <= ~sel_b; + end +endmodule
diff --git a/axi2sramcrs/rtl/share/axi_slice/axi_fwd_regd_slice.v b/axi2sramcrs/rtl/share/axi_slice/axi_fwd_regd_slice.v new file mode 100644 index 0000000..a4ee8d8 --- /dev/null +++ b/axi2sramcrs/rtl/share/axi_slice/axi_fwd_regd_slice.v
@@ -0,0 +1,75 @@ +//**************************************************************************** +// +// Copyright 2017-2023 Vivante Corporation +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +//**************************************************************************** +// Auto-generated file on 11/03/2023. +// +//**************************************************************************** + +module axi_fwd_regd_slice + ( + aresetn, + aclk, + valid_src, + ready_dst, + payload_src, + ready_src, + valid_dst, + payload_dst + ); + parameter PAYLD_WIDTH = 2; + parameter PAYLD_MAX = (PAYLD_WIDTH - 1); + input aresetn; + input aclk; + input valid_src; + input ready_dst; + input [PAYLD_MAX:0] payload_src; + output valid_dst; + output ready_src; + output [PAYLD_MAX:0] payload_dst; + wire aresetn; + wire aclk; + wire valid_src; + wire ready_dst; + wire [PAYLD_MAX:0] payload_src; + wire valid_dst; + wire ready_src; + reg [PAYLD_MAX:0] payload_dst; + wire payload_en; + wire valid_dst_en; + reg ivalid_dst; + assign valid_dst = ivalid_dst; + assign ready_src = ready_dst | ~ivalid_dst; + //end + always @(posedge aclk or negedge aresetn) + begin : p_payload_dst + if (~aresetn) + payload_dst <= {PAYLD_WIDTH{1'b0}}; + else if (payload_en) + payload_dst <= payload_src; + end + assign payload_en = ((valid_src & ~ivalid_dst) | + (valid_src & ivalid_dst & ready_dst)); + assign valid_dst_en = (valid_src | ready_dst); + always @(posedge aclk or negedge aresetn) + begin : p_ivalid_dst + if (~aresetn) + ivalid_dst <= 1'b0; + else if (valid_dst_en) + ivalid_dst <= valid_src; + end + +endmodule
diff --git a/axi2sramcrs/rtl/share/axi_slice/axi_rev_regd_slice.v b/axi2sramcrs/rtl/share/axi_slice/axi_rev_regd_slice.v new file mode 100644 index 0000000..5d83b7e --- /dev/null +++ b/axi2sramcrs/rtl/share/axi_slice/axi_rev_regd_slice.v
@@ -0,0 +1,84 @@ +//**************************************************************************** +// +// Copyright 2017-2023 Vivante Corporation +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +//**************************************************************************** +// Auto-generated file on 11/03/2023. +// +//**************************************************************************** + +module axi_rev_regd_slice + ( + aresetn, + aclk, + valid_src, + ready_dst, + payload_src, + valid_dst, + ready_src, + payload_dst + ); + parameter PAYLD_WIDTH = 1; + parameter PAYLD_MAX = PAYLD_WIDTH - 1; + parameter NUM_SEL_LINES = (PAYLD_WIDTH + 7) / 8; + parameter REM_SEL_LINE = (((PAYLD_WIDTH - 1) % 8) + 1); + input aclk; + input aresetn; + input [PAYLD_MAX:0] payload_src; + output [PAYLD_MAX:0] payload_dst; + input valid_src; + output ready_src; + output valid_dst; + input ready_dst; + reg [PAYLD_MAX:0] payload_dst; + reg [PAYLD_MAX:0] payload_reg; + wire buffer_en; + wire buffer_full_en; + reg [NUM_SEL_LINES:0] buffer_full; + assign buffer_en = (valid_src & ~buffer_full[0] & ~ready_dst); + always @(negedge aresetn or posedge aclk) + begin : p_buffer_seq + if (~aresetn) + payload_reg <= {PAYLD_WIDTH{1'b0}}; + else if (buffer_en) + payload_reg <= payload_src; + end + assign buffer_full_en = (buffer_en | ready_dst); + always @(negedge aresetn or posedge aclk) + begin : p_buffer_full_seq + if (~aresetn) + buffer_full <= {NUM_SEL_LINES+1{1'b0}}; + else if (buffer_full_en) + buffer_full <= {NUM_SEL_LINES+1{buffer_en}}; + end + assign ready_src = ~buffer_full[0]; + assign valid_dst = (valid_src | buffer_full[0]); + always @(buffer_full or payload_reg or payload_src) + begin : p_payload_mux + integer i; + integer j; + integer base; + base = 0; + for (i=1; i<NUM_SEL_LINES; i=i+1) + begin + for (j=base; j<(base+8); j=j+1) + payload_dst[j] = (buffer_full[i] ? payload_reg[j] : payload_src[j]); + base = (8 * i); + end + for (j=base; j<(base+REM_SEL_LINE); j=j+1) + payload_dst[j] = (buffer_full[NUM_SEL_LINES] ? payload_reg[j] + : payload_src[j]); + end +endmodule
diff --git a/axi2sramcrs/rtl/share/axi_slice/axi_slice.v b/axi2sramcrs/rtl/share/axi_slice/axi_slice.v new file mode 100644 index 0000000..6cc3875 --- /dev/null +++ b/axi2sramcrs/rtl/share/axi_slice/axi_slice.v
@@ -0,0 +1,111 @@ +//**************************************************************************** +// +// Copyright 2017-2023 Vivante Corporation +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +//**************************************************************************** +// Auto-generated file on 11/03/2023. +// +//**************************************************************************** + +`include "defs_axi_slice.v" +module axi_slice + ( + aresetn, + aclk, + src_data, + src_valid, + src_ready, + dst_data, + dst_valid, + dst_ready + ); + parameter HNDSHK_MODE = `RS_REV_REG; + parameter PAYLD_WIDTH = 12; + parameter PAYLD_MAX = (PAYLD_WIDTH - 1); + parameter INT_HNDSHK_MODE = HNDSHK_MODE; + + input aresetn; + input aclk; + input [PAYLD_MAX:0] src_data; + output [PAYLD_MAX:0] dst_data; + input src_valid; + output src_ready; + output dst_valid; + input dst_ready; + wire [PAYLD_MAX:0] payld_src; + wire [PAYLD_MAX:0] payld_regd; + wire [PAYLD_MAX:0] payld_fwd_regd; + wire [PAYLD_MAX:0] payld_rev_regd; + wire valid_regd; + wire valid_fwd_regd; + wire valid_rev_regd; + wire ready_regd; + wire ready_fwd_regd; + wire ready_rev_regd; + assign src_ready = ((INT_HNDSHK_MODE == `RS_REGD) ? ready_regd + :((INT_HNDSHK_MODE == `RS_FWD_REG) ? ready_fwd_regd + :((INT_HNDSHK_MODE == `RS_REV_REG) ? ready_rev_regd + : dst_ready))); + assign dst_data = ((INT_HNDSHK_MODE == `RS_REGD) ? payld_regd + :((INT_HNDSHK_MODE == `RS_FWD_REG) ? payld_fwd_regd + :((INT_HNDSHK_MODE == `RS_REV_REG) ? payld_rev_regd + : src_data))); + assign dst_valid = ((INT_HNDSHK_MODE == `RS_REGD) ? valid_regd + :((INT_HNDSHK_MODE == `RS_FWD_REG) ? valid_fwd_regd + :((INT_HNDSHK_MODE == `RS_REV_REG) ? valid_rev_regd + : src_valid))); + assign payld_src = src_data; + axi_ful_regd_slice #( + .PAYLD_WIDTH (PAYLD_WIDTH) + ) u_ful_regd_slice + ( + .aresetn (aresetn), + .aclk (aclk), + .valid_src (src_valid), + .ready_dst (dst_ready), + .payload_src (payld_src), + .ready_src (ready_regd), + .valid_dst (valid_regd), + .payload_dst (payld_regd) + ); + axi_fwd_regd_slice #( + .PAYLD_WIDTH(PAYLD_WIDTH) + ) u_fwd_regd_slice + ( + .aresetn (aresetn), + .aclk (aclk), + .valid_src (src_valid), + .ready_dst (dst_ready), + .payload_src (payld_src), + .ready_src (ready_fwd_regd), + .valid_dst (valid_fwd_regd), + .payload_dst (payld_fwd_regd) + ); + axi_rev_regd_slice #( + .PAYLD_WIDTH(PAYLD_WIDTH) + ) u_rev_regd_slice + ( + .aresetn (aresetn), + .aclk (aclk), + .valid_src (src_valid), + .ready_dst (dst_ready), + .payload_src (payld_src), + .ready_src (ready_rev_regd), + .valid_dst (valid_rev_regd), + .payload_dst (payld_rev_regd) + ); + +endmodule +`include "undefs_axi_slice.v"
diff --git a/axi2sramcrs/rtl/share/axi_slice/defs_axi_slice.v b/axi2sramcrs/rtl/share/axi_slice/defs_axi_slice.v new file mode 100644 index 0000000..8772649 --- /dev/null +++ b/axi2sramcrs/rtl/share/axi_slice/defs_axi_slice.v
@@ -0,0 +1,25 @@ +//**************************************************************************** +// +// Copyright 2017-2023 Vivante Corporation +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +//**************************************************************************** +// Auto-generated file on 11/03/2023. +// +//**************************************************************************** + +`define RS_REGD 0 +`define RS_FWD_REG 1 +`define RS_REV_REG 2 +`define RS_STATIC_BYPASS 3
diff --git a/axi2sramcrs/rtl/share/axi_slice/undefs_axi_slice.v b/axi2sramcrs/rtl/share/axi_slice/undefs_axi_slice.v new file mode 100644 index 0000000..e597cde --- /dev/null +++ b/axi2sramcrs/rtl/share/axi_slice/undefs_axi_slice.v
@@ -0,0 +1,25 @@ +//**************************************************************************** +// +// Copyright 2017-2023 Vivante Corporation +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +//**************************************************************************** +// Auto-generated file on 11/03/2023. +// +//**************************************************************************** + +`undef RS_REGD +`undef RS_FWD_REG +`undef RS_REV_REG +`undef RS_STATIC_BYPASS
diff --git a/axi2sramcrs/rtl/upsizer/axi_upsizer.v b/axi2sramcrs/rtl/upsizer/axi_upsizer.v new file mode 100644 index 0000000..8bbaac0 --- /dev/null +++ b/axi2sramcrs/rtl/upsizer/axi_upsizer.v
@@ -0,0 +1,339 @@ +//**************************************************************************** +// +// Copyright 2017-2023 Vivante Corporation +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +//**************************************************************************** +// Auto-generated file on 11/03/2023. +// +//**************************************************************************** + +module axi_upsizer( + awid_m, awaddr_m, awlen_m, awsize_m, awburst_m, awlock_m, + awcache_m, awprot_m, awvalid_m, awuser_m, awregion_m, wdata_m, + wstrb_m, wlast_m, wvalid_m, wid_m, wuser_m, bready_m, arid_m, + araddr_m, arlen_m, arsize_m, arburst_m, arlock_m, arcache_m, + arprot_m, arvalid_m, aruser_m, arregion_m, rready_m, awqos_m, + arqos_m, awready_s, wready_s, bid_s, bresp_s, bvalid_s, buser_s, + arready_s, rid_s, rdata_s, rresp_s, rlast_s, rvalid_s, ruser_s, + aclk, aresetn, awready_m, wready_m, bid_m, bresp_m, bvalid_m, + buser_m, arready_m, rid_m, rdata_m, rresp_m, rlast_m, rvalid_m, + ruser_m, awid_s, awaddr_s, awlen_s, awsize_s, awburst_s, awlock_s, + awcache_s, awprot_s, awvalid_s, awuser_s, awregion_s, wdata_s, + wstrb_s, wlast_s, wvalid_s, wid_s, wuser_s, bready_s, arid_s, + araddr_s, arlen_s, arsize_s, arburst_s, arlock_s, arcache_s, + arprot_s, arvalid_s, aruser_s, arregion_s, rready_s, awqos_s, + arqos_s + ); +parameter ARID_WIDTH=16; +parameter AWID_WIDTH=16; +parameter ADDR_WIDTH=61; +parameter US_DATA_WIDTH=64; +parameter DS_DATA_WIDTH=256; +parameter USER_WIDTH=16; +parameter IS_AXI3=1'h1; +parameter RD_ISS=128; +parameter WR_ISS=128; +parameter DS_WSTRB_WIDTH=DS_DATA_WIDTH/8; +parameter US_WSTRB_WIDTH=US_DATA_WIDTH/8; +localparam AXLEN_WIDTH=(IS_AXI3==1'h1) ? 4 : 8; +localparam DS_AXI3=IS_AXI3; +localparam DS_ADDR_AL_WIDTH=$clog2(DS_WSTRB_WIDTH); +localparam US_ADDR_AL_WIDTH=$clog2(US_WSTRB_WIDTH); +localparam ARFMT_WIDTH=1+1+ARID_WIDTH+DS_ADDR_AL_WIDTH*3+1+3; +localparam AWFMT_WIDTH=AWID_WIDTH+1+4+1+DS_ADDR_AL_WIDTH*2+3+1; +localparam US_AW_WIDTH=4+USER_WIDTH+AWID_WIDTH+ADDR_WIDTH+8+3+2+2+4+4+3+1; +localparam US_AR_WIDTH=4+USER_WIDTH+ARID_WIDTH+ADDR_WIDTH+8+3+2+2+4+4+3+1; +localparam US_R_WIDTH=USER_WIDTH+ARID_WIDTH+US_DATA_WIDTH+2+1; +localparam US_W_WIDTH=USER_WIDTH+AWID_WIDTH+US_DATA_WIDTH+US_WSTRB_WIDTH+1; +localparam US_B_WIDTH=USER_WIDTH+AWID_WIDTH+2; +localparam AW_IDB_WIDTH=US_AW_WIDTH; +localparam AR_IDB_WIDTH=US_AR_WIDTH; +localparam W_IDB_WIDTH=AWID_WIDTH+USER_WIDTH+DS_DATA_WIDTH+DS_WSTRB_WIDTH+1; +localparam R_IDB_WIDTH=USER_WIDTH+ARID_WIDTH+DS_DATA_WIDTH+2+1; +localparam B_IDB_WIDTH=USER_WIDTH+2+AWID_WIDTH; +input aclk; +input aresetn; + output [AWID_WIDTH-1:0] awid_m; + output [ADDR_WIDTH-1:0] awaddr_m; + output [AXLEN_WIDTH-1:0] awlen_m; + output [2:0] awsize_m; + output [1:0] awburst_m; + output [1:0] awlock_m; + output [3:0] awcache_m; + output [2:0] awprot_m; + output awvalid_m; + input awready_m; + output [USER_WIDTH-1:0] awuser_m; + output [3:0] awregion_m; + output [DS_DATA_WIDTH-1:0] wdata_m; + output [DS_WSTRB_WIDTH-1:0] wstrb_m; + output wlast_m; + output wvalid_m; + input wready_m; + output [AWID_WIDTH-1:0] wid_m; + output [USER_WIDTH-1:0] wuser_m; + input [AWID_WIDTH-1:0] bid_m; + input [1:0] bresp_m; + input bvalid_m; + output bready_m; + input [USER_WIDTH-1:0] buser_m; + output [ARID_WIDTH-1:0] arid_m; + output [ADDR_WIDTH-1:0] araddr_m; + output [AXLEN_WIDTH-1:0] arlen_m; + output [2:0] arsize_m; + output [1:0] arburst_m; + output [1:0] arlock_m; + output [3:0] arcache_m; + output [2:0] arprot_m; + output arvalid_m; + input arready_m; + output [USER_WIDTH-1:0] aruser_m; + output [3:0] arregion_m; + input [ARID_WIDTH-1:0] rid_m; + input [DS_DATA_WIDTH-1:0] rdata_m; + input [1:0] rresp_m; + input rlast_m; + input rvalid_m; + output rready_m; + input [USER_WIDTH-1:0] ruser_m; + output [3:0] awqos_m; + output [3:0] arqos_m; + input [AWID_WIDTH-1:0] awid_s; + input [ADDR_WIDTH-1:0] awaddr_s; + input [AXLEN_WIDTH-1:0] awlen_s; + input [2:0] awsize_s; + input [1:0] awburst_s; + input [1:0] awlock_s; + input [3:0] awcache_s; + input [2:0] awprot_s; + input awvalid_s; + output awready_s; + input [USER_WIDTH-1:0] awuser_s; + input [3:0] awregion_s; + input [US_DATA_WIDTH-1:0] wdata_s; + input [US_WSTRB_WIDTH-1:0] wstrb_s; + input wlast_s; + input wvalid_s; + output wready_s; + input [AWID_WIDTH-1:0] wid_s; + input [USER_WIDTH-1:0] wuser_s; + output [AWID_WIDTH-1:0] bid_s; + output [1:0] bresp_s; + output bvalid_s; + input bready_s; + output [USER_WIDTH-1:0] buser_s; + input [ARID_WIDTH-1:0] arid_s; + input [ADDR_WIDTH-1:0] araddr_s; + input [AXLEN_WIDTH-1:0] arlen_s; + input [2:0] arsize_s; + input [1:0] arburst_s; + input [1:0] arlock_s; + input [3:0] arcache_s; + input [2:0] arprot_s; + input arvalid_s; + output arready_s; + input [USER_WIDTH-1:0] aruser_s; + input [3:0] arregion_s; + output [ARID_WIDTH-1:0] rid_s; + output [US_DATA_WIDTH-1:0] rdata_s; + output [1:0] rresp_s; + output rlast_s; + output rvalid_s; + input rready_s; + output [USER_WIDTH-1:0] ruser_s; + input [3:0] awqos_s; + input [3:0] arqos_s; +wire [AR_IDB_WIDTH-1:0] ar_data; +wire ar_ready; +wire ar_valid; +wire [AW_IDB_WIDTH-1:0] aw_data; +wire aw_ready; +wire aw_valid; +wire [B_IDB_WIDTH-1:0] b_data; +wire b_ready; +wire b_valid; +wire [R_IDB_WIDTH-1:0] r_data; +wire r_ready; +wire r_valid; +wire [W_IDB_WIDTH-1:0] w_data; +wire w_ready; +wire w_valid; +wire [7:0] arlen_s_ext; +wire [7:0] awlen_s_ext; +wire [7:0] arlen_m_ext; +wire [7:0] awlen_m_ext; +generate + if(AXLEN_WIDTH==8) begin + assign arlen_s_ext=arlen_s; + assign awlen_s_ext=awlen_s; + assign arlen_m=arlen_m_ext; + assign awlen_m=awlen_m_ext; + end + else begin + assign arlen_s_ext={4'h0,arlen_s}; + assign awlen_s_ext={4'h0,awlen_s}; + assign arlen_m=arlen_m_ext[3:0]; + assign awlen_m=awlen_m_ext[3:0]; + end +endgenerate +upsize_slave_domain #( + .ARID_WIDTH (ARID_WIDTH), + .AWID_WIDTH (AWID_WIDTH), + .ADDR_WIDTH (ADDR_WIDTH), + .US_DATA_WIDTH (US_DATA_WIDTH), + .DS_DATA_WIDTH (DS_DATA_WIDTH), + .USER_WIDTH (USER_WIDTH), + .RD_ISS (RD_ISS), + .WR_ISS (WR_ISS), + .DS_AXI3 (DS_AXI3)) + u_slave_domain( + .arqv_s (arqos_s), + .awqv_s (awqos_s), + .awlen_s (awlen_s_ext), + .arlen_s (arlen_s_ext), + .awvalid_vect_s(1'h0), + .arvalid_vect_s(1'h0), + .awready_s (awready_s), + .wready_s (wready_s), + .bid_s (bid_s[AWID_WIDTH-1:0]), + .bresp_s (bresp_s[1:0]), + .bvalid_s (bvalid_s), + .buser_s (buser_s[USER_WIDTH-1:0]), + .arready_s (arready_s), + .rid_s (rid_s[ARID_WIDTH-1:0]), + .rdata_s (rdata_s[US_DATA_WIDTH-1:0]), + .rresp_s (rresp_s[1:0]), + .rlast_s (rlast_s), + .rvalid_s (rvalid_s), + .ruser_s (ruser_s[USER_WIDTH-1:0]), + .aw_data (aw_data[AW_IDB_WIDTH-1:0]), + .aw_valid (aw_valid), + .b_ready (b_ready), + .ar_data (ar_data[AR_IDB_WIDTH-1:0]), + .ar_valid (ar_valid), + .r_ready (r_ready), + .w_data (w_data[W_IDB_WIDTH-1:0]), + .w_valid (w_valid), + .awid_s (awid_s[AWID_WIDTH-1:0]), + .awaddr_s (awaddr_s[ADDR_WIDTH-1:0]), + .awsize_s (awsize_s[2:0]), + .awburst_s (awburst_s[1:0]), + .awlock_s (awlock_s[1:0]), + .awcache_s (awcache_s[3:0]), + .awprot_s (awprot_s[2:0]), + .awvalid_s (awvalid_s), + .awuser_s (awuser_s[USER_WIDTH-1:0]), + .awregion_s (awregion_s[3:0]), + .wdata_s (wdata_s[US_DATA_WIDTH-1:0]), + .wstrb_s (wstrb_s[US_WSTRB_WIDTH-1:0]), + .wlast_s (wlast_s), + .wvalid_s (wvalid_s), + .wid_s (wid_s[AWID_WIDTH-1:0]), + .wuser_s (wuser_s[USER_WIDTH-1:0]), + .bready_s (bready_s), + .arid_s (arid_s[ARID_WIDTH-1:0]), + .araddr_s (araddr_s[ADDR_WIDTH-1:0]), + .arsize_s (arsize_s[2:0]), + .arburst_s (arburst_s[1:0]), + .arlock_s (arlock_s[1:0]), + .arcache_s (arcache_s[3:0]), + .arprot_s (arprot_s[2:0]), + .arvalid_s (arvalid_s), + .aruser_s (aruser_s[USER_WIDTH-1:0]), + .arregion_s (arregion_s[3:0]), + .rready_s (rready_s), + .aw_ready (aw_ready), + .b_data (b_data[B_IDB_WIDTH-1:0]), + .b_valid (b_valid), + .ar_ready (ar_ready), + .r_data (r_data[R_IDB_WIDTH-1:0]), + .r_valid (r_valid), + .w_ready (w_ready), + .aclk (aclk), + .aresetn (aresetn)); +upsize_master_domain #( + .ARID_WIDTH (ARID_WIDTH), + .AWID_WIDTH (AWID_WIDTH), + .ADDR_WIDTH (ADDR_WIDTH), + .US_DATA_WIDTH (US_DATA_WIDTH), + .DS_DATA_WIDTH (DS_DATA_WIDTH), + .USER_WIDTH (USER_WIDTH), + .RD_ISS (RD_ISS), + .WR_ISS (WR_ISS)) u_master_domain( + .awqv_m (awqos_m), + .arqv_m (arqos_m), + .arlen_m (arlen_m_ext), + .awlen_m (awlen_m_ext), + .awvalid_vect_m (), + .arvalid_vect_m (), + .awid_m (awid_m[AWID_WIDTH-1:0]), + .awaddr_m (awaddr_m[ADDR_WIDTH-1:0]), + .awsize_m (awsize_m[2:0]), + .awburst_m (awburst_m[1:0]), + .awlock_m (awlock_m[1:0]), + .awcache_m (awcache_m[3:0]), + .awprot_m (awprot_m[2:0]), + .awvalid_m (awvalid_m), + .awuser_m (awuser_m[USER_WIDTH-1:0]), + .awregion_m (awregion_m[3:0]), + .wdata_m (wdata_m[DS_DATA_WIDTH-1:0]), + .wstrb_m (wstrb_m[DS_WSTRB_WIDTH-1:0]), + .wlast_m (wlast_m), + .wvalid_m (wvalid_m), + .wid_m (wid_m[AWID_WIDTH-1:0]), + .wuser_m (wuser_m[USER_WIDTH-1:0]), + .bready_m (bready_m), + .arid_m (arid_m[ARID_WIDTH-1:0]), + .araddr_m (araddr_m[ADDR_WIDTH-1:0]), + .arsize_m (arsize_m[2:0]), + .arburst_m (arburst_m[1:0]), + .arlock_m (arlock_m[1:0]), + .arcache_m (arcache_m[3:0]), + .arprot_m (arprot_m[2:0]), + .arvalid_m (arvalid_m), + .aruser_m (aruser_m[USER_WIDTH-1:0]), + .arregion_m (arregion_m[3:0]), + .rready_m (rready_m), + .aw_ready (aw_ready), + .b_data (b_data[B_IDB_WIDTH-1:0]), + .b_valid (b_valid), + .ar_ready (ar_ready), + .r_data (r_data[R_IDB_WIDTH-1:0]), + .r_valid (r_valid), + .w_ready (w_ready), + .awready_m (awready_m), + .wready_m (wready_m), + .bid_m (bid_m[AWID_WIDTH-1:0]), + .bresp_m (bresp_m[1:0]), + .bvalid_m (bvalid_m), + .buser_m (buser_m[USER_WIDTH-1:0]), + .arready_m (arready_m), + .rid_m (rid_m[ARID_WIDTH-1:0]), + .rdata_m (rdata_m[DS_DATA_WIDTH-1:0]), + .rresp_m (rresp_m[1:0]), + .rlast_m (rlast_m), + .rvalid_m (rvalid_m), + .ruser_m (ruser_m[USER_WIDTH-1:0]), + .aw_data (aw_data[AW_IDB_WIDTH-1:0]), + .aw_valid (aw_valid), + .b_ready (b_ready), + .ar_data (ar_data[AR_IDB_WIDTH-1:0]), + .ar_valid (ar_valid), + .r_ready (r_ready), + .w_data (w_data[W_IDB_WIDTH-1:0]), + .w_valid (w_valid), + .aclk (aclk), + .aresetn (aresetn)); +endmodule
diff --git a/axi2sramcrs/rtl/upsizer/maskcntl.v b/axi2sramcrs/rtl/upsizer/maskcntl.v new file mode 100644 index 0000000..ab3fbf2 --- /dev/null +++ b/axi2sramcrs/rtl/upsizer/maskcntl.v
@@ -0,0 +1,303 @@ +//**************************************************************************** +// +// Copyright 2017-2023 Vivante Corporation +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +//**************************************************************************** +// Auto-generated file on 11/03/2023. +// +//**************************************************************************** +//========================================================================= +//==maskcntl: mask the incoming transctions to garantee the outgoing outstanding transactions +//====meet the outstanding configs +//========================================================================= +module maskcntl + ( + // Master Interface address channel handshake signals + awvalid_m, + awready_m, + arvalid_m, + arready_m, + // Lock control signals + pre_awvalid, + pre_arvalid, + awlock, + arlock, + lock_seq, + // QoS input signals + aw_qos_s, + ar_qos_s, + // Master Interface return channel handshake signals + bvalid_m, + bready_m, + rvalid_m, + rready_m, + // Mask signals + wr_cnt_empty, + mask_w, + mask_r, + // QoS output signals + aw_qos_m, + ar_qos_m, + // Miscellaneous connections + aclk, + aresetn + ); + + // --------------------------------------------------------------------------- + // parameters + // --------------------------------------------------------------------------- +//read outstanding issues +parameter RD_ISS=8; +//write outstanding issues +parameter WR_ISS=8; + +localparam RCNT_WIDTH=$clog2(RD_ISS+1); +localparam WCNT_WIDTH=$clog2(WR_ISS+1); +localparam COMBCNT_WIDTH=(RCNT_WIDTH>WCNT_WIDTH) ? (RCNT_WIDTH+1) : (WCNT_WIDTH+1); + // --------------------------------------------------------------------------- + // Port definitions + // --------------------------------------------------------------------------- + + // Master Interface address channel handshake signals + input awvalid_m; + input awready_m; + input arvalid_m; + input arready_m; + // Lock control signals + input pre_awvalid; + input pre_arvalid; + input awlock; + input arlock; + // QoS input signals + input [3:0] aw_qos_s; + input [3:0] ar_qos_s; + // Master Interface return channel handshake signals + input bvalid_m; + input bready_m; + input rvalid_m; + input rready_m; + // Mask signals + output wr_cnt_empty; + output mask_w; + output mask_r; + // QoS output signals + output [3:0] aw_qos_m; + output [3:0] ar_qos_m; + // Lock sequence signal + output lock_seq; + // Miscelaneous connections + input aclk; + input aresetn; + + //------------------------------------------------------------------------------ + // Wires + //------------------------------------------------------------------------------ + + wire push_rd; // Read address accepted; + wire push_wr; // Write address accepted + wire pop_rd; // Last read beat accepted + wire pop_wr; // Write transaction accepted + wire next_wr_cnt_empty; // Next Write counter empty + wire wr_cnt_en; + wire rd_cnt_en; + wire comb_cnt_en; + wire wr_mask_en; + wire rd_mask_en; + wire [RCNT_WIDTH-1:0] next_rd_cnt; // next outstanding reads count + wire [WCNT_WIDTH-1:0] next_wr_cnt; // next outstanding writes count + reg [COMBCNT_WIDTH-1:0] next_comb_cnt; // next outstanding trans count + reg [WCNT_WIDTH-1:0] wr_iss_d; + reg [RCNT_WIDTH-1:0] rd_iss_d; + reg next_mask_w; + reg next_mask_r; + + wire nxt_lock_seq; + wire lock_seq_en; + + wire [3:0] aw_qos_s; + wire [3:0] ar_qos_s; + + + //------------------------------------------------------------------------------ + // Registers + //------------------------------------------------------------------------------ + + reg [RCNT_WIDTH-1:0] rd_cnt; // outstanding reads count + reg [WCNT_WIDTH-1:0] wr_cnt; // outstanding writes count + reg [COMBCNT_WIDTH-1:0] comb_cnt; // outstanding trans count + reg lock_seq; + reg wr_cnt_empty; // Write counter empty + reg reg_mask_w; + reg reg_mask_r; + + // --------------------------------------------------------------------------- + // start of code + // --------------------------------------------------------------------------- + + //---------------------------- Drive QoS outputs ---------------------------- + + + // Pass through input Qos Value + assign aw_qos_m = aw_qos_s; + assign ar_qos_m = ar_qos_s; + + + //-------------------- Outstanding transaction counters --------------------- + + assign push_rd = arvalid_m & arready_m; + assign push_wr = awvalid_m & awready_m; + + assign pop_rd = rvalid_m & rready_m; + assign pop_wr = bvalid_m & bready_m; + + // Determine next outstanding read counter + assign next_rd_cnt = (push_rd & ~pop_rd) ? rd_cnt + 1'b1 + : ((~push_rd & pop_rd) ? rd_cnt - 1'b1 + : rd_cnt); + + // Determine next outstanding write counter + assign next_wr_cnt = (push_wr & ~pop_wr) ? wr_cnt + 1'b1 + : ((~push_wr & pop_wr) ? wr_cnt - 1'b1 + : wr_cnt); + + // Determine next combined outstanding counter + always @(*) + begin : p_next_comb + case({push_wr, push_rd, pop_wr, pop_rd}) + 4'b0001, + 4'b0010, + 4'b0111, + 4'b1011 : next_comb_cnt = (comb_cnt - 2'h1); + 4'b0011 : next_comb_cnt = (comb_cnt - 2'h2); + 4'b0100, + 4'b1000, + 4'b1101, + 4'b1110 : next_comb_cnt = (comb_cnt + 2'h1); + 4'b1100 : next_comb_cnt = (comb_cnt + 2'h2); + default : next_comb_cnt = comb_cnt; + endcase + end // p_next_comb + + + + + assign wr_cnt_en = push_wr ^ pop_wr; + assign rd_cnt_en = push_rd ^ pop_rd; + assign comb_cnt_en = push_wr | push_rd | pop_wr | pop_rd; + + assign next_wr_cnt_empty = (next_wr_cnt == 1'b0); + + always @(posedge aclk or negedge aresetn) + begin : p_wr_cnt_seq + if (!aresetn) + begin + wr_cnt <= {WCNT_WIDTH{1'b0}}; + wr_cnt_empty <= 1'b1; + rd_cnt <= {RCNT_WIDTH{1'b0}}; + comb_cnt <= {3{1'b0}}; + end + else + begin + if (wr_cnt_en) + begin + wr_cnt <= next_wr_cnt; + wr_cnt_empty <= next_wr_cnt_empty; + end + if (rd_cnt_en) + begin + rd_cnt <= next_rd_cnt; + end + if (comb_cnt_en) + begin + comb_cnt <= next_comb_cnt; + end + end + end // p_wr_cnt_seq + + //--------------------------- Mask Generation ------------------------------- + + always @(next_wr_cnt or next_rd_cnt) + begin : p_mask_comb + wr_iss_d = WR_ISS; + rd_iss_d = RD_ISS; + + next_mask_w = 1'b0; + next_mask_r = 1'b0; + + // If the next write count will be reached then + // mask all the write slave interfaces + if (next_wr_cnt == wr_iss_d ) + next_mask_w = 1'b1; + // If the next read count will be reached then + // mask all the read slave interfaces + if (next_rd_cnt == rd_iss_d ) + next_mask_r = 1'b1; + end // p_mask_comb + + + + assign wr_mask_en =push_wr | pop_wr; + assign rd_mask_en = push_rd | pop_rd; + + always @(posedge aclk or negedge aresetn) + begin : p_wr_mask_seq + if (!aresetn) + begin + reg_mask_w <= 1'b0; + end + else if (wr_mask_en) + begin + reg_mask_w <= next_mask_w; + end + end // p_wr_mask_seq + + assign mask_w = reg_mask_w; + + always @(posedge aclk or negedge aresetn) + begin : p_rd_mask_seq + if (!aresetn) + begin + reg_mask_r <= 1'b0; + end + else if (rd_mask_en) + begin + reg_mask_r <= next_mask_r; + end + end // p_rd_mask_seq + + assign mask_r = reg_mask_r; + //--------------------------- Lock Seq Register ------------------------------- + + assign nxt_lock_seq = ((pre_awvalid & awlock) | (pre_arvalid & arlock)) + ? 1'b1 + : (((pre_awvalid & ~awlock) | (pre_arvalid & ~arlock)) & ~|comb_cnt + ? 1'b0 + : lock_seq); + + assign lock_seq_en = pre_awvalid || pre_arvalid; + + always @(posedge aclk or negedge aresetn) + begin : p_lock_seq + if (!aresetn) + begin + lock_seq <= 1'b0; + end + else if (lock_seq_en) + begin + lock_seq <= nxt_lock_seq; + end + end // p_lock_seq + + endmodule
diff --git a/axi2sramcrs/rtl/upsizer/upsize_master_domain.v b/axi2sramcrs/rtl/upsizer/upsize_master_domain.v new file mode 100644 index 0000000..a3565fe --- /dev/null +++ b/axi2sramcrs/rtl/upsizer/upsize_master_domain.v
@@ -0,0 +1,233 @@ +//**************************************************************************** +// +// Copyright 2017-2023 Vivante Corporation +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +//**************************************************************************** +// Auto-generated file on 11/03/2023. +// +//**************************************************************************** + +`include "Axi.v" +module upsize_master_domain + ( + awid_m, awaddr_m, awlen_m, awsize_m, awburst_m, awlock_m, + awcache_m, awprot_m, awvalid_m, awvalid_vect_m, awuser_m, + awregion_m, wdata_m, wstrb_m, wlast_m, wvalid_m, wid_m, wuser_m, + bready_m, arid_m, araddr_m, arlen_m, arsize_m, arburst_m, arlock_m, + arcache_m, arprot_m, arvalid_m, arvalid_vect_m, aruser_m, + arregion_m, rready_m, awqv_m, arqv_m, aw_ready, b_data, b_valid, + ar_ready, r_data, r_valid, w_ready, + awready_m, wready_m, bid_m, bresp_m, bvalid_m, buser_m, arready_m, + rid_m, rdata_m, rresp_m, rlast_m, rvalid_m, ruser_m, aw_data, + aw_valid, b_ready, ar_data, ar_valid, r_ready, w_data, w_valid, + aclk, aresetn + ); +parameter ARID_WIDTH=4; +parameter AWID_WIDTH=4; +parameter ADDR_WIDTH=32; +parameter US_DATA_WIDTH=128; +parameter DS_DATA_WIDTH=256; +parameter USER_WIDTH=4; +parameter RD_ISS=8; +parameter WR_ISS=8; +localparam DS_WSTRB_WIDTH=DS_DATA_WIDTH/8; +localparam US_WSTRB_WIDTH=US_DATA_WIDTH/8; +localparam DS_ADDR_AL_WIDTH=$clog2(DS_WSTRB_WIDTH); +localparam US_ADDR_AL_WIDTH=$clog2(US_WSTRB_WIDTH); +localparam ARFMT_WIDTH=1+1+ARID_WIDTH+DS_ADDR_AL_WIDTH*3+1+3; +localparam AWFMT_WIDTH=AWID_WIDTH+1+4+1+DS_ADDR_AL_WIDTH*2+3+1; +localparam US_AW_WIDTH=4+USER_WIDTH+AWID_WIDTH+ADDR_WIDTH+8+3+2+2+4+4+3+1; +localparam US_AR_WIDTH=4+USER_WIDTH+ARID_WIDTH+ADDR_WIDTH+8+3+2+2+4+4+3+1; +localparam US_R_WIDTH=USER_WIDTH+ARID_WIDTH+US_DATA_WIDTH+2+1; +localparam US_W_WIDTH=USER_WIDTH+AWID_WIDTH+US_DATA_WIDTH+US_WSTRB_WIDTH+1; +localparam US_B_WIDTH=USER_WIDTH+AWID_WIDTH+2; +localparam AW_IDB_WIDTH=US_AW_WIDTH; +localparam AR_IDB_WIDTH=US_AR_WIDTH; +localparam W_IDB_WIDTH=AWID_WIDTH+USER_WIDTH+DS_DATA_WIDTH+DS_WSTRB_WIDTH+1; +localparam R_IDB_WIDTH=USER_WIDTH+ARID_WIDTH+DS_DATA_WIDTH+2+1; +localparam B_IDB_WIDTH=USER_WIDTH+2+AWID_WIDTH; + output [AWID_WIDTH-1:0] awid_m; + output [ADDR_WIDTH-1:0] awaddr_m; + output [7:0] awlen_m; + output [2:0] awsize_m; + output [1:0] awburst_m; + output [1:0] awlock_m; + output [3:0] awcache_m; + output [2:0] awprot_m; + output awvalid_m; + output awvalid_vect_m; + input awready_m; + output [USER_WIDTH-1:0] awuser_m; + output [3:0] awregion_m; + output [DS_DATA_WIDTH-1:0] wdata_m; + output [DS_WSTRB_WIDTH-1:0] wstrb_m; + output wlast_m; + output wvalid_m; + input wready_m; + output [AWID_WIDTH-1:0] wid_m; + output [USER_WIDTH-1:0] wuser_m; + input [AWID_WIDTH-1:0] bid_m; + input [1:0] bresp_m; + input bvalid_m; + output bready_m; + input [USER_WIDTH-1:0] buser_m; + output [ARID_WIDTH-1:0] arid_m; + output [ADDR_WIDTH-1:0] araddr_m; + output [7:0] arlen_m; + output [2:0] arsize_m; + output [1:0] arburst_m; + output [1:0] arlock_m; + output [3:0] arcache_m; + output [2:0] arprot_m; + output arvalid_m; + output arvalid_vect_m; + input arready_m; + output [USER_WIDTH-1:0] aruser_m; + output [3:0] arregion_m; + input [ARID_WIDTH-1:0] rid_m; + input [DS_DATA_WIDTH-1:0] rdata_m; + input [1:0] rresp_m; + input rlast_m; + input rvalid_m; + output rready_m; + input [USER_WIDTH-1:0] ruser_m; + output [3:0] awqv_m; + output [3:0] arqv_m; + input [AW_IDB_WIDTH-1:0] aw_data; + input aw_valid; + output aw_ready; + output [B_IDB_WIDTH-1:0] b_data; + output b_valid; + input b_ready; + input [AR_IDB_WIDTH-1:0] ar_data; + input ar_valid; + output ar_ready; + output [R_IDB_WIDTH-1:0] r_data; + output r_valid; + input r_ready; + input [W_IDB_WIDTH-1:0] w_data; + input w_valid; + output w_ready; + input aclk; + input aresetn; + wire awvalid_master; + wire awready_master; + wire arvalid_master; + wire arready_master; + wire bvalid_master; + wire bready_master; + wire rvalid_master; + wire awvalid_vector; + wire arvalid_vector; + wire wr_cnt_empty; + wire mask_w; + wire mask_r; + wire [3:0] aw_qos_s; + wire [3:0] ar_qos_s; + wire awvalid_lock; + wire arvalid_lock; + wire lock_seq; + assign { + awregion_m, + awuser_m, + awid_m, + awaddr_m, + awlen_m, + awsize_m, + awburst_m, + awlock_m, + awcache_m, + aw_qos_s, + awprot_m, + awvalid_vector} = aw_data; + assign awvalid_master = aw_valid; + assign aw_ready = awready_master; + assign { + arregion_m, + aruser_m, + arid_m, + araddr_m, + arlen_m, + arsize_m, + arburst_m, + arlock_m, + arcache_m, + ar_qos_s, + arprot_m, + arvalid_vector} = ar_data; + assign arvalid_master= ar_valid; + assign ar_ready = arready_master; + assign { + wid_m, + wuser_m, + wdata_m, + wstrb_m, + wlast_m} = w_data; + assign wvalid_m= w_valid; + assign w_ready = wready_m; + assign r_data = { + ruser_m, + rid_m, + rdata_m, + rresp_m, + rlast_m}; + assign r_valid = rvalid_m; + assign rready_m= r_ready; + assign b_data = { + buser_m, + bid_m, + bresp_m}; + assign b_valid = bvalid_master; + assign bready_master = b_ready; +maskcntl #( + .RD_ISS(RD_ISS), + .WR_ISS(WR_ISS) + ) u_maskcntl ( + .awvalid_m (awvalid_master), + .arvalid_m (arvalid_master), + .awready_m (awready_master), + .arready_m (arready_master), + .aw_qos_s (aw_qos_s), + .ar_qos_s (ar_qos_s), + .bvalid_m (bvalid_master), + .bready_m (bready_master), + .rvalid_m (rvalid_master), + .rready_m (rready_m), + .pre_awvalid (awvalid_master), + .pre_arvalid (arvalid_master), + .awlock (awlock_m[1]), + .arlock (arlock_m[1]), + .lock_seq (lock_seq), + .wr_cnt_empty (wr_cnt_empty), + .mask_w (mask_w), + .mask_r (mask_r), + .aw_qos_m (awqv_m), + .ar_qos_m (arqv_m), + .aclk (aclk), + .aresetn (aresetn) + ); + assign awvalid_lock = (awvalid_master & awlock_m[1]); + assign arvalid_lock = (arvalid_master & arlock_m[1]); + assign awvalid_m = ~mask_w & ((awvalid_master & ~lock_seq) | awvalid_lock); + assign arvalid_m = ~mask_r & ((arvalid_master & ~lock_seq) | arvalid_lock); + assign awready_master = (awready_m & (~lock_seq | (awvalid_master & awlock_m[1])) & !mask_w); + assign arready_master = (arready_m & (~lock_seq | (arvalid_master & arlock_m[1])) & !mask_r); + assign bvalid_master = (bvalid_m & !wr_cnt_empty); + assign bready_m = (bready_master & !wr_cnt_empty); + assign rvalid_master = rvalid_m & rlast_m; + assign awvalid_vect_m = ({1{awvalid_m}} & awvalid_vector); + assign arvalid_vect_m = ({1{arvalid_m}} & arvalid_vector); +endmodule +`include "Axi_undefs.v"
diff --git a/axi2sramcrs/rtl/upsizer/upsize_rd_addr_fmt.v b/axi2sramcrs/rtl/upsizer/upsize_rd_addr_fmt.v new file mode 100644 index 0000000..6f5ab9d --- /dev/null +++ b/axi2sramcrs/rtl/upsizer/upsize_rd_addr_fmt.v
@@ -0,0 +1,774 @@ +//**************************************************************************** +// +// Copyright 2017-2023 Vivante Corporation +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +//**************************************************************************** +// Auto-generated file on 11/03/2023. +// +//**************************************************************************** + +module upsize_rd_addr_fmt + ( + ar_lock_hndshk, ar_unlock_hndshk, ardata_valid, ardata_data, + arready_s, arid_m, araddr_m, arlen_m, arsize_m, arburst_m, + arcache_m, arprot_m, arlock_m, arvalid_m, aruser_m, arregion_m, + aclk, aresetn, lock_seq, ardata_ready, arid_s, araddr_s, arlen_s, + arsize_s, arburst_s, arcache_s, arprot_s, arvalid_s, arlock_s, + aruser_s, arregion_s, arready_m + ); +`include "Axi.v" +parameter ARID_WIDTH=4; +parameter AWID_WIDTH=4; +parameter ADDR_WIDTH=32; +parameter US_DATA_WIDTH=128; +parameter DS_DATA_WIDTH=256; +parameter USER_WIDTH=4; +parameter DS_AXI3=1'h1; +localparam US_AXLEN_WIDTH=8; +localparam DS_AXLEN_WIDTH=8; +localparam DS_WSTRB_WIDTH=DS_DATA_WIDTH/8; +localparam US_WSTRB_WIDTH=US_DATA_WIDTH/8; +localparam DS_ADDR_AL_WIDTH=$clog2(DS_WSTRB_WIDTH); +localparam US_ADDR_AL_WIDTH=$clog2(US_WSTRB_WIDTH); +localparam ARFMT_WIDTH=1+1+ARID_WIDTH+DS_ADDR_AL_WIDTH*3+1+3; +localparam US_AW_WIDTH=4+USER_WIDTH+AWID_WIDTH+ADDR_WIDTH+8+3+2+2+4+4+3+1; +localparam US_AR_WIDTH=4+USER_WIDTH+ARID_WIDTH+ADDR_WIDTH+8+3+2+2+4+4+3+1; +localparam US_R_WIDTH=USER_WIDTH+ARID_WIDTH+US_DATA_WIDTH+2+1; +localparam US_W_WIDTH=USER_WIDTH+AWID_WIDTH+US_DATA_WIDTH+US_WSTRB_WIDTH+1; +localparam US_B_WIDTH=USER_WIDTH+AWID_WIDTH+2; +localparam AW_IDB_WIDTH=US_AW_WIDTH+US_ADDR_AL_WIDTH-DS_ADDR_AL_WIDTH; +localparam AR_IDB_WIDTH=US_AR_WIDTH+ARFMT_WIDTH; +localparam W_IDB_WIDTH=USER_WIDTH+US_DATA_WIDTH+US_WSTRB_WIDTH+1; +localparam R_IDB_WIDTH=USER_WIDTH+ARID_WIDTH+US_DATA_WIDTH+2+1+DS_ADDR_AL_WIDTH; +localparam B_IDB_WIDTH=USER_WIDTH+2+AWID_WIDTH; +localparam RDATA_CAM_WIDTH_UP =DS_ADDR_AL_WIDTH-US_ADDR_AL_WIDTH; +localparam TOTAL_BYTES_WIDTH = US_ADDR_AL_WIDTH+8; + input aclk; + input aresetn; + input lock_seq; + output ar_lock_hndshk; + output ar_unlock_hndshk; + input ardata_ready; + output ardata_valid; + output [ARFMT_WIDTH-1:0] ardata_data; + input [ARID_WIDTH-1:0] arid_s; + input [ADDR_WIDTH-1:0] araddr_s; + input [US_AXLEN_WIDTH-1:0] arlen_s; + input [2:0] arsize_s; + input [1:0] arburst_s; + input [3:0] arcache_s; + input [2:0] arprot_s; + input arvalid_s; + input [1:0] arlock_s; + output arready_s; + input [USER_WIDTH-1:0] aruser_s; + input [3:0] arregion_s; + output [ARID_WIDTH-1:0] arid_m; + output [ADDR_WIDTH-1:0] araddr_m; + output [DS_AXLEN_WIDTH-1:0] arlen_m; + output [2:0] arsize_m; + output [1:0] arburst_m; + output [3:0] arcache_m; + output [2:0] arprot_m; + output [1:0] arlock_m; + output arvalid_m; + input arready_m; + output [USER_WIDTH-1:0] aruser_m; + output [3:0] arregion_m; + reg [ADDR_WIDTH-1:0] araddro; // transaction start address (int) + reg [7:0] arleno; // transaction length (int) + reg [2:0] arsizeo; // transaction transfer size (int) + reg [1:0] arbursto; // transaction burst type (int) + reg [ARID_WIDTH-1:0] arido; + reg [3:0] arcacheo; + reg [2:0] arproto; + reg [1:0] arlocko; + reg [USER_WIDTH-1:0] arusero; + reg [3:0] arregiono; + reg excl_override_reg; + reg busy_reg; + reg [TOTAL_BYTES_WIDTH-1:0] wrap_bytes_remaining_reg; + reg [DS_ADDR_AL_WIDTH-1:0] align_mask; + reg [DS_ADDR_AL_WIDTH-1:0] read_mask; + wire n_response; + reg [TOTAL_BYTES_WIDTH-1:0] total_bytes; + reg [TOTAL_BYTES_WIDTH-1:0] total_bytes_masked; + reg [2:0] wrapsize; + reg [2:0] wrapfitsize; + reg [3:0] wraplen; + reg [DS_ADDR_AL_WIDTH:0] wrapalignmask; + reg wrap_split_reg; + reg [2:0] incrsize; + wire slave_hndshk; + wire master_hndshk; + wire bypass; + wire [ADDR_WIDTH-1:0] araddr_aligned; + wire [DS_ADDR_AL_WIDTH+8-1:0] total_bytes_ext; + wire [TOTAL_BYTES_WIDTH-1:0] wrap_boundary_mask; + wire wrap_aligned; + wire wrap_is_incr; + wire wrap_split; + wire wrap_fits; + wire [TOTAL_BYTES_WIDTH-1:0] wrap_fits_mask; + wire [DS_ADDR_AL_WIDTH:0] working_addr; + wire wrap_split_reg_nxt; + wire wrap_split_reg_wr_en; + wire wrap_info_write_en; + wire [TOTAL_BYTES_WIDTH-1:0] next_wrap_bytes_remaining_reg; + wire [TOTAL_BYTES_WIDTH-1:0] addr_less_one; + wire [7:0] wraplen_i; + wire [7:0] arlen_1; + wire [7:0] incrlen; + wire [TOTAL_BYTES_WIDTH-1:0] bytes_to_transfer; + wire [TOTAL_BYTES_WIDTH+8-1:0] bytes_to_transfer_large; + wire [TOTAL_BYTES_WIDTH-1:0] bytes_to_transfer_wrap1; + wire [DS_ADDR_AL_WIDTH-1:0] offset_address; + wire [7:0] incrlenmaxsize; + wire [DS_ADDR_AL_WIDTH:0] final_address; + wire overflow; + wire bytes_lt_one_byte; + wire bytes_lt_two_byte; + wire bytes_lt_two_half; + wire bytes_lt_four_half; + wire half_carry; + wire half_carry_double; + wire bytes_lt_four_word; + wire bytes_lt_eight_word; + wire [2:0] word_carry; + wire word_carry_double; + wire bytes_lt_eight_dword; + wire bytes_lt_sixt_dword; + wire [3:0] dword_carry; + wire dword_carry_double; + wire bytes_lt_sixt_qword; + wire bytes_lt_ttwo_qword; + wire [4:0] qword_carry; + wire qword_carry_double; + wire bytes_lt_ttwo_oword; + wire bytes_lt_sfour_oword; + wire [5:0] oword_carry; + wire oword_carry_double; + wire buffers_ok; + wire new_transaction; + wire trans_in_progress; + wire new_trans_avail; + wire trans_complete; + wire next_busy_reg; + wire busy_reg_wr_en; + wire excl_override; + assign slave_hndshk = arvalid_s & arready_s; + assign master_hndshk = arvalid_m & arready_m; +assign ardata_data = { + wrap_fits, + n_response, + arid_s, + ((arburst_s == `AXI_ABURST_WRAP) & ~wrap_is_incr) ? addr_less_one[DS_ADDR_AL_WIDTH-1:0] & align_mask : final_address[DS_ADDR_AL_WIDTH-1:0] & align_mask, + read_mask, + araddr_s[DS_ADDR_AL_WIDTH-1:0] & align_mask, + bypass, + arsize_s + }; + assign ardata_valid = new_transaction; + always @(*) + begin : p_new_addr_incr_en_r + read_mask = {DS_ADDR_AL_WIDTH{1'b0}}; + case (arburst_s) + `AXI_ABURST_FIXED : read_mask = {DS_ADDR_AL_WIDTH{1'b0}}; + `AXI_ABURST_WRAP : read_mask = total_bytes[DS_ADDR_AL_WIDTH-1:0]; + `AXI_ABURST_INCR : read_mask = {DS_ADDR_AL_WIDTH{1'b1}}; + default : read_mask = {DS_ADDR_AL_WIDTH{1'b0}}; + endcase + end + assign n_response = wrap_split; + assign buffers_ok = ardata_ready; + assign trans_complete = ~(wrap_split & ~wrap_split_reg); + assign trans_in_progress = new_transaction | busy_reg; + assign new_transaction = new_trans_avail & buffers_ok; + assign new_trans_avail = arvalid_s & ~busy_reg; + assign next_busy_reg = (trans_complete & slave_hndshk) ? 1'b0 : + ((new_transaction & ~slave_hndshk) ? 1'b1 : busy_reg); + assign busy_reg_wr_en = busy_reg ^ next_busy_reg; + always @(posedge aclk or negedge aresetn) + begin : busy_reg_p + if (!aresetn) begin + busy_reg <= 1'b0; + end else if (busy_reg_wr_en) begin + busy_reg <= next_busy_reg; + end + end + assign excl_override = (new_transaction) ? n_response | (|arleno[7:4]) : excl_override_reg; + always @(posedge aclk or negedge aresetn) + begin : excl_override_reg_p + if (!aresetn) begin + excl_override_reg <= 1'b0; + end else if (new_transaction) begin + excl_override_reg <= excl_override; + end + end + assign arid_m = arido; + assign arcache_m = arcacheo; + assign arprot_m = arproto; + assign arlen_m = arleno; + assign arsize_m = arsizeo; + assign araddr_m = araddro; + assign arburst_m = arbursto; + assign arlock_m = arlocko; + assign aruser_m = arusero; + assign arregion_m = arregiono; + assign arvalid_m = arvalid_s && trans_in_progress; + assign arready_s = master_hndshk && trans_complete; + always @(*) begin + arleno = incrlen; + arsizeo = incrsize; + arbursto = `AXI_ABURST_INCR; + arido = arid_s; + arcacheo = arcache_s; + arproto = arprot_s; + arusero = aruser_s; + arregiono = arregion_s; + araddro = araddr_aligned; + arlocko = {(arlock_s[1] | (lock_seq & ~trans_complete)),(arlock_s[0] && (~excl_override))}; + if (!wrap_split_reg) begin + araddro = araddr_s; + if (wrap_aligned) begin + arleno = wraplen_i; + arsizeo = wrapsize; + arbursto = `AXI_ABURST_WRAP; + end else if (bypass) begin + arleno = arlen_s; + arsizeo = arsize_s; + arbursto = arburst_s; + end else if (wrap_fits) begin + araddro = araddr_aligned; + arleno = arlen_1; + arsizeo = wrapfitsize; + arbursto = `AXI_ABURST_INCR; + end + end + end + assign wraplen_i = {4'b0000,wraplen}; + assign arlen_1 = {4'b0000,`AXI_ALEN_1}; + assign addr_less_one = araddr_s[TOTAL_BYTES_WIDTH-1:0] - {{TOTAL_BYTES_WIDTH{1'b0}},1'b1}; + assign next_wrap_bytes_remaining_reg = (addr_less_one & total_bytes); + assign wrap_info_write_en = wrap_split & master_hndshk; + always @(posedge aclk or negedge aresetn) + begin : wrap_bytes_remaining_reg_p + if (!aresetn) begin + wrap_bytes_remaining_reg <= {TOTAL_BYTES_WIDTH{1'b0}}; + end else if (wrap_info_write_en) begin + wrap_bytes_remaining_reg <= next_wrap_bytes_remaining_reg; + end + end + assign araddr_aligned = {araddr_s[ADDR_WIDTH-1:TOTAL_BYTES_WIDTH],((araddr_s[TOTAL_BYTES_WIDTH-1:0]) & (~total_bytes))}; + assign wrap_split_reg_nxt = wrap_split & ~(wrap_split_reg); + assign wrap_split_reg_wr_en = master_hndshk; + always @(posedge aclk or negedge aresetn) + begin : wrap_split_p + if (!aresetn) + wrap_split_reg <= 1'b0; + else if (wrap_split_reg_wr_en) + wrap_split_reg <= wrap_split_reg_nxt; + end + assign ar_lock_hndshk = (slave_hndshk & arlock_s[1]); + assign ar_unlock_hndshk = (master_hndshk & ~arlock_m[1]); + assign bypass = (arburst_s == `AXI_ABURST_FIXED ) || ~arcache_s[1] || (arlen_s == `AXI_ALEN_1); + +generate + +if(TOTAL_BYTES_WIDTH == 10) begin: tb10 +always @(*) + begin : total_bytes_p + case (arsize_s) + `AXI_ASIZE_8 : total_bytes = {2'h0, arlen_s}; + `AXI_ASIZE_16 : total_bytes = {1'h0, arlen_s, 1'b1}; + `AXI_ASIZE_32 : total_bytes = { arlen_s, 2'b11}; + `AXI_ASIZE_64 : total_bytes = { arlen_s[6:0], 3'b111}; + `AXI_ASIZE_128 : total_bytes = { arlen_s[5:0], 4'b1111}; + `AXI_ASIZE_256 : total_bytes = { arlen_s[4:0], 5'b11111}; + `AXI_ASIZE_512 : total_bytes = { arlen_s[3:0], 6'b111111}; + `AXI_ASIZE_1024 : total_bytes = {2'h0, arlen_s}; + default : total_bytes = {10'hx}; + endcase + end +end +else if(TOTAL_BYTES_WIDTH == 11) begin: tb11 +always @(*) + begin : total_bytes_p + case (arsize_s) + `AXI_ASIZE_8 : total_bytes = {3'b0, arlen_s}; + `AXI_ASIZE_16 : total_bytes = {2'b0, arlen_s, 1'b1}; + `AXI_ASIZE_32 : total_bytes = {1'b0, arlen_s, 2'b11}; + `AXI_ASIZE_64 : total_bytes = { arlen_s, 3'b111}; + `AXI_ASIZE_128 : total_bytes = { arlen_s[6:0], 4'b1111}; + `AXI_ASIZE_256 : total_bytes = { arlen_s[5:0], 5'b11111}; + `AXI_ASIZE_512 : total_bytes = { arlen_s[4:0], 6'b111111}; + `AXI_ASIZE_1024 : total_bytes = {3'b0, arlen_s}; + default : total_bytes = {11'b0}; + endcase + end + +end +else if(TOTAL_BYTES_WIDTH == 12) begin: tb12 +always @(*) + begin : total_bytes_p + case (arsize_s) + `AXI_ASIZE_8 : total_bytes = {4'b0, arlen_s}; + `AXI_ASIZE_16 : total_bytes = {3'b0, arlen_s, 1'b1}; + `AXI_ASIZE_32 : total_bytes = {2'b0, arlen_s, 2'b11}; + `AXI_ASIZE_64 : total_bytes = {1'b0, arlen_s, 3'b111}; + `AXI_ASIZE_128 : total_bytes = { arlen_s, 4'b1111}; + `AXI_ASIZE_256 : total_bytes = { arlen_s[6:0], 5'b11111}; + `AXI_ASIZE_512 : total_bytes = { arlen_s[5:0], 6'b111111}; + `AXI_ASIZE_1024 : total_bytes = {4'b0, arlen_s}; + default : total_bytes = {12'b0}; + endcase + end + +end +else if(TOTAL_BYTES_WIDTH == 13) begin: tb13 +always @(*) + begin : total_bytes_p + case (arsize_s) + `AXI_ASIZE_8 : total_bytes = {5'b0, arlen_s}; + `AXI_ASIZE_16 : total_bytes = {4'b0, arlen_s, 1'b1}; + `AXI_ASIZE_32 : total_bytes = {3'b0, arlen_s, 2'b11}; + `AXI_ASIZE_64 : total_bytes = {2'b0, arlen_s, 3'b111}; + `AXI_ASIZE_128 : total_bytes = {1'b0, arlen_s, 4'b1111}; + `AXI_ASIZE_256 : total_bytes = { arlen_s, 5'b11111}; + `AXI_ASIZE_512 : total_bytes = { arlen_s[6:0], 6'b111111}; + `AXI_ASIZE_1024 : total_bytes = {5'b0, arlen_s}; + default : total_bytes = {13'b0}; + endcase + end + +end + +else begin: tb_o + +always @(*) + begin : total_bytes_p + case (arsize_s) + `AXI_ASIZE_8 : total_bytes = {6'b0, arlen_s}; + `AXI_ASIZE_16 : total_bytes = {5'b0, arlen_s, 1'b1}; + `AXI_ASIZE_32 : total_bytes = {4'b0, arlen_s, 2'b11}; + `AXI_ASIZE_64 : total_bytes = {3'b0, arlen_s, 3'b111}; + `AXI_ASIZE_128 : total_bytes = {2'b0, arlen_s, 4'b1111}; + `AXI_ASIZE_256 : total_bytes = {1'b0, arlen_s, 5'b11111}; + `AXI_ASIZE_512 : total_bytes = { arlen_s, 6'b111111}; + `AXI_ASIZE_1024 : total_bytes = {6'b0, arlen_s}; + default : total_bytes = {14'b0}; + endcase + end + +end + +endgenerate + + + assign total_bytes_ext = { {RDATA_CAM_WIDTH_UP{1'b0}},total_bytes }; + + +generate + +if(DS_DATA_WIDTH==512) begin: wmsk_512 + +always @(*) + begin : wrap_size_len + if (total_bytes_ext[6]&&(DS_DATA_WIDTH>=512)) begin + wrapfitsize = `AXI_ASIZE_1024; + wrapsize = `AXI_ASIZE_512; + wraplen = total_bytes_ext[9:6]; + wrapalignmask = {1'b0, 6'b111111}; + end else if (total_bytes_ext[5]&&(DS_DATA_WIDTH>=256)) begin + wrapfitsize = `AXI_ASIZE_512; + wrapsize = `AXI_ASIZE_256; + wraplen = total_bytes_ext[8:5]; + wrapalignmask = {2'b0, 5'b11111}; + end else if (total_bytes_ext[4]&&(DS_DATA_WIDTH>=128)) begin + wrapfitsize = `AXI_ASIZE_256; + wrapsize = `AXI_ASIZE_128; + wraplen = total_bytes_ext[7:4]; + wrapalignmask = {3'b0, 4'b1111}; + end else if (total_bytes_ext[3]&&(DS_DATA_WIDTH>=64)) begin + wrapfitsize = `AXI_ASIZE_128; + wrapsize = `AXI_ASIZE_64; + wraplen = total_bytes_ext[6:3]; + wrapalignmask = {4'b0, 3'b111}; + end else if (total_bytes_ext[2]&&(DS_DATA_WIDTH>=32)) begin + wrapfitsize = `AXI_ASIZE_64; + wrapsize = `AXI_ASIZE_32; + wraplen = total_bytes_ext[5:2]; + wrapalignmask = {5'b0, 2'b11}; + end else if (total_bytes_ext[1]&&(DS_DATA_WIDTH>=16)) begin + wrapfitsize = `AXI_ASIZE_32; + wrapsize = `AXI_ASIZE_16; + wraplen = total_bytes_ext[4:1]; + wrapalignmask = {6'b0, 1'b1}; + end else if (total_bytes_ext[0]&&(DS_DATA_WIDTH>=8))begin + wrapfitsize = `AXI_ASIZE_16; + wrapsize = `AXI_ASIZE_8; + wraplen = total_bytes_ext[3:0]; + wrapalignmask = 7'b0; + end else begin + wrapfitsize = 3'b0; + wrapsize = 3'b0; + wraplen = 4'b0; + wrapalignmask = 7'b0; + end + end + +end + +if(DS_DATA_WIDTH==256) begin: wmsk_256 + +always @(*) + begin : wrap_size_len + if (total_bytes_ext[5]&&(DS_DATA_WIDTH>=256)) begin + wrapfitsize = `AXI_ASIZE_512; + wrapsize = `AXI_ASIZE_256; + wraplen = total_bytes_ext[8:5]; + wrapalignmask = {2'b0, 5'b11111}; + end else if (total_bytes_ext[4]&&(DS_DATA_WIDTH>=128)) begin + wrapfitsize = `AXI_ASIZE_256; + wrapsize = `AXI_ASIZE_128; + wraplen = total_bytes_ext[7:4]; + wrapalignmask = {3'b0, 4'b1111}; + end else if (total_bytes_ext[3]&&(DS_DATA_WIDTH>=64)) begin + wrapfitsize = `AXI_ASIZE_128; + wrapsize = `AXI_ASIZE_64; + wraplen = total_bytes_ext[6:3]; + wrapalignmask = {4'b0, 3'b111}; + end else if (total_bytes_ext[2]&&(DS_DATA_WIDTH>=32)) begin + wrapfitsize = `AXI_ASIZE_64; + wrapsize = `AXI_ASIZE_32; + wraplen = total_bytes_ext[5:2]; + wrapalignmask = {5'b0, 2'b11}; + end else if (total_bytes_ext[1]&&(DS_DATA_WIDTH>=16)) begin + wrapfitsize = `AXI_ASIZE_32; + wrapsize = `AXI_ASIZE_16; + wraplen = total_bytes_ext[4:1]; + wrapalignmask = {6'b0, 1'b1}; + end else if (total_bytes_ext[0]&&(DS_DATA_WIDTH>=8))begin + wrapfitsize = `AXI_ASIZE_16; + wrapsize = `AXI_ASIZE_8; + wraplen = total_bytes_ext[3:0]; + wrapalignmask = 7'b0; + end else begin + wrapfitsize = 3'b0;//x; + wrapsize = 3'b0;//x; + wraplen = 4'b0;//x; + wrapalignmask = 7'b0;//x; + end + end + +end + +if(DS_DATA_WIDTH==128) begin: wmsk_128 + +always @(*) + begin : wrap_size_len + if (total_bytes_ext[4]&&(DS_DATA_WIDTH>=128)) begin + wrapfitsize = `AXI_ASIZE_256; + wrapsize = `AXI_ASIZE_128; + wraplen = total_bytes_ext[7:4]; + wrapalignmask = {3'b0, 4'b1111}; + end else if (total_bytes_ext[3]&&(DS_DATA_WIDTH>=64)) begin + wrapfitsize = `AXI_ASIZE_128; + wrapsize = `AXI_ASIZE_64; + wraplen = total_bytes_ext[6:3]; + wrapalignmask = {4'b0, 3'b111}; + end else if (total_bytes_ext[2]&&(DS_DATA_WIDTH>=32)) begin + wrapfitsize = `AXI_ASIZE_64; + wrapsize = `AXI_ASIZE_32; + wraplen = total_bytes_ext[5:2]; + wrapalignmask = {5'b0, 2'b11}; + end else if (total_bytes_ext[1]&&(DS_DATA_WIDTH>=16)) begin + wrapfitsize = `AXI_ASIZE_32; + wrapsize = `AXI_ASIZE_16; + wraplen = total_bytes_ext[4:1]; + wrapalignmask = {6'b0, 1'b1}; + end else if (total_bytes_ext[0]&&(DS_DATA_WIDTH>=8))begin + wrapfitsize = `AXI_ASIZE_16; + wrapsize = `AXI_ASIZE_8; + wraplen = total_bytes_ext[3:0]; + wrapalignmask = 7'b0; + end else begin + wrapfitsize = 3'b0;//x; + wrapsize = 3'b0;//x; + wraplen = 4'b0;//x; + wrapalignmask = 7'b0;//x; + end + end + +end +if(DS_DATA_WIDTH==64) begin: wmsk_64 + +always @(*) + begin : wrap_size_len + if (total_bytes_ext[3]&&(DS_DATA_WIDTH>=64)) begin + wrapfitsize = `AXI_ASIZE_128; + wrapsize = `AXI_ASIZE_64; + wraplen = total_bytes_ext[6:3]; + wrapalignmask = {4'b0, 3'b111}; + end else if (total_bytes_ext[2]&&(DS_DATA_WIDTH>=32)) begin + wrapfitsize = `AXI_ASIZE_64; + wrapsize = `AXI_ASIZE_32; + wraplen = total_bytes_ext[5:2]; + wrapalignmask = {5'b0, 2'b11}; + end else if (total_bytes_ext[1]&&(DS_DATA_WIDTH>=16)) begin + wrapfitsize = `AXI_ASIZE_32; + wrapsize = `AXI_ASIZE_16; + wraplen = total_bytes_ext[4:1]; + wrapalignmask = {6'b0, 1'b1}; + end else if (total_bytes_ext[0]&&(DS_DATA_WIDTH>=8))begin + wrapfitsize = `AXI_ASIZE_16; + wrapsize = `AXI_ASIZE_8; + wraplen = total_bytes_ext[3:0]; + wrapalignmask = 7'b0; + end else begin + wrapfitsize = 3'b0; + wrapsize = 3'b0; + wraplen = 4'b0; + wrapalignmask = 7'b0; + end + end + +end + +if(DS_DATA_WIDTH==32) begin: wmsk_32 + +always @(*) + begin : wrap_size_len + if (total_bytes_ext[2]&&(DS_DATA_WIDTH>=32)) begin + wrapfitsize = `AXI_ASIZE_64; + wrapsize = `AXI_ASIZE_32; + wraplen = total_bytes_ext[5:2]; + wrapalignmask = {5'b0, 2'b11}; + end else if (total_bytes_ext[1]&&(DS_DATA_WIDTH>=16)) begin + wrapfitsize = `AXI_ASIZE_32; + wrapsize = `AXI_ASIZE_16; + wraplen = total_bytes_ext[4:1]; + wrapalignmask = {6'b0, 1'b1}; + end else if (total_bytes_ext[0]&&(DS_DATA_WIDTH>=8))begin + wrapfitsize = `AXI_ASIZE_16; + wrapsize = `AXI_ASIZE_8; + wraplen = total_bytes_ext[3:0]; + wrapalignmask = 7'b0; + end else begin + wrapfitsize = 3'b0; + wrapsize = 3'b0; + wraplen = 4'b0; + wrapalignmask = 7'b0; + end + end + +end + +endgenerate + + + assign working_addr = araddr_s[DS_ADDR_AL_WIDTH:0] & wrapalignmask; + assign wrap_fits_mask = ({(TOTAL_BYTES_WIDTH-DS_ADDR_AL_WIDTH){1'b1}}<<DS_ADDR_AL_WIDTH); + assign wrap_fits = ~|(total_bytes & wrap_fits_mask) & (arburst_s == `AXI_ABURST_WRAP); + assign wrap_is_incr = ~|(araddr_s[TOTAL_BYTES_WIDTH-1:0] & total_bytes); + assign wrap_aligned = ~|working_addr & (arburst_s == `AXI_ABURST_WRAP) & ~bypass & ~wrap_is_incr & ~wrap_fits ; + assign wrap_split = ((|working_addr)) & (arburst_s == `AXI_ABURST_WRAP) & ~bypass & ~wrap_fits; + assign wrap_boundary_mask = total_bytes; + assign bytes_to_transfer_wrap1 = ~(araddr_s[TOTAL_BYTES_WIDTH-1:0]) & wrap_boundary_mask; + assign bytes_to_transfer = (wrap_split_reg) ? wrap_bytes_remaining_reg + : ((arburst_s == `AXI_ABURST_WRAP) ? bytes_to_transfer_wrap1 + : total_bytes_masked); +generate +if(TOTAL_BYTES_WIDTH == 10) begin:tbm10 +always @(*) + begin : total_bytes_masked_p + case (arsize_s) + `AXI_ASIZE_8 : total_bytes_masked = { 2'h0, arlen_s}; + `AXI_ASIZE_16 : total_bytes_masked = { 1'h0, arlen_s, ~araddr_s[0]}; + `AXI_ASIZE_32 : total_bytes_masked = { arlen_s, ~araddr_s[1:0]}; + `AXI_ASIZE_64 : total_bytes_masked = { arlen_s[6:0], ~araddr_s[2:0]}; + `AXI_ASIZE_128 : total_bytes_masked = { arlen_s[5:0], ~araddr_s[3:0]}; + `AXI_ASIZE_256 : total_bytes_masked = { arlen_s[4:0], ~araddr_s[4:0]}; + `AXI_ASIZE_512 : total_bytes_masked = { arlen_s[3:0], ~araddr_s[5:0]}; + `AXI_ASIZE_1024 : total_bytes_masked = { 2'h0, arlen_s}; + default : total_bytes_masked = {10{1'b0}}; + endcase + end +end + + +else if(TOTAL_BYTES_WIDTH == 11) begin:tbm11 +always @(*) + begin : total_bytes_masked_p + case (arsize_s) + `AXI_ASIZE_8 : total_bytes_masked = { 3'h0, arlen_s}; + `AXI_ASIZE_16 : total_bytes_masked = { 2'h0, arlen_s, ~araddr_s[0]}; + `AXI_ASIZE_32 : total_bytes_masked = { 1'h0, arlen_s, ~araddr_s[1:0]}; + `AXI_ASIZE_64 : total_bytes_masked = { arlen_s, ~araddr_s[2:0]}; + `AXI_ASIZE_128 : total_bytes_masked = { arlen_s[6:0], ~araddr_s[3:0]}; + `AXI_ASIZE_256 : total_bytes_masked = { arlen_s[5:0], ~araddr_s[4:0]}; + `AXI_ASIZE_512 : total_bytes_masked = { arlen_s[4:0], ~araddr_s[5:0]}; + `AXI_ASIZE_1024 : total_bytes_masked = { 3'h0, arlen_s}; + default : total_bytes_masked = {11{1'b0}}; + endcase + end +end + + +else if(TOTAL_BYTES_WIDTH == 12) begin:tbm12 +always @(*) + begin : total_bytes_masked_p + case (arsize_s) + `AXI_ASIZE_8 : total_bytes_masked = { 4'h0, arlen_s}; + `AXI_ASIZE_16 : total_bytes_masked = { 3'h0, arlen_s, ~araddr_s[0]}; + `AXI_ASIZE_32 : total_bytes_masked = { 2'h0, arlen_s, ~araddr_s[1:0]}; + `AXI_ASIZE_64 : total_bytes_masked = { 1'b0, arlen_s, ~araddr_s[2:0]}; + `AXI_ASIZE_128 : total_bytes_masked = { arlen_s, ~araddr_s[3:0]}; + `AXI_ASIZE_256 : total_bytes_masked = { arlen_s[6:0], ~araddr_s[4:0]}; + `AXI_ASIZE_512 : total_bytes_masked = { arlen_s[5:0], ~araddr_s[5:0]}; + `AXI_ASIZE_1024 : total_bytes_masked = { 4'h0, arlen_s}; + default : total_bytes_masked = {12{1'b0}}; + endcase + end +end + + +else if(TOTAL_BYTES_WIDTH == 13) begin:tbm13 +always @(*) + begin : total_bytes_masked_p + case (arsize_s) + `AXI_ASIZE_8 : total_bytes_masked = { 5'h0, arlen_s}; + `AXI_ASIZE_16 : total_bytes_masked = { 4'h0, arlen_s, ~araddr_s[0]}; + `AXI_ASIZE_32 : total_bytes_masked = { 3'h0, arlen_s, ~araddr_s[1:0]}; + `AXI_ASIZE_64 : total_bytes_masked = { 2'h0, arlen_s, ~araddr_s[2:0]}; + `AXI_ASIZE_128 : total_bytes_masked = { 1'h0, arlen_s, ~araddr_s[3:0]}; + `AXI_ASIZE_256 : total_bytes_masked = { arlen_s, ~araddr_s[4:0]}; + `AXI_ASIZE_512 : total_bytes_masked = { arlen_s[6:0], ~araddr_s[5:0]}; + `AXI_ASIZE_1024 : total_bytes_masked = { 5'h0, arlen_s}; + default : total_bytes_masked = {13{1'b0}}; + endcase + end +end + + +else begin:tbm_o +always @(*) + begin : total_bytes_masked_p + case (arsize_s) + `AXI_ASIZE_8 : total_bytes_masked = { 6'h0, arlen_s}; + `AXI_ASIZE_16 : total_bytes_masked = { 5'h0, arlen_s, ~araddr_s[0]}; + `AXI_ASIZE_32 : total_bytes_masked = { 4'h0, arlen_s, ~araddr_s[1:0]}; + `AXI_ASIZE_64 : total_bytes_masked = { 3'h0, arlen_s, ~araddr_s[2:0]}; + `AXI_ASIZE_128 : total_bytes_masked = { 2'h0, arlen_s, ~araddr_s[3:0]}; + `AXI_ASIZE_256 : total_bytes_masked = { 1'h0, arlen_s, ~araddr_s[4:0]}; + `AXI_ASIZE_512 : total_bytes_masked = { arlen_s, ~araddr_s[5:0]}; + `AXI_ASIZE_1024 : total_bytes_masked = { 6'h0, arlen_s}; + default : total_bytes_masked = {14{1'b0}}; + endcase + end +end + + +endgenerate + + + + + always @(*) + begin : align_mask_p + case (arsize_s) + `AXI_ASIZE_8 : align_mask = {DS_ADDR_AL_WIDTH{1'b1}}; + `AXI_ASIZE_16 : align_mask = {DS_ADDR_AL_WIDTH{1'b1}}<<1; + `AXI_ASIZE_32 : align_mask = {DS_ADDR_AL_WIDTH{1'b1}}<<2; + `AXI_ASIZE_64 : align_mask = {DS_ADDR_AL_WIDTH{1'b1}}<<3; + `AXI_ASIZE_128 : align_mask = {DS_ADDR_AL_WIDTH{1'b1}}<<4; + `AXI_ASIZE_256 : align_mask = {DS_ADDR_AL_WIDTH{1'b1}}<<5; + `AXI_ASIZE_512 : align_mask = {DS_ADDR_AL_WIDTH{1'b1}}<<6; + default : align_mask = {DS_ADDR_AL_WIDTH{1'b0}}; + endcase + end + assign offset_address = (wrap_split_reg) ? araddr_aligned[DS_ADDR_AL_WIDTH-1:0] : + araddr_s[DS_ADDR_AL_WIDTH-1:0]; + assign half_carry = bytes_to_transfer[0] & offset_address[0]; + assign half_carry_double = half_carry & bytes_to_transfer[1]; + assign word_carry = {1'b0, bytes_to_transfer[1:0]} + {1'b0, offset_address[1:0]}; + assign word_carry_double = word_carry[2] & bytes_to_transfer[2]; +generate + if(DS_DATA_WIDTH>=64) begin: dword_carry_64 + assign dword_carry = {1'b0, bytes_to_transfer[2:0]} + {1'b0, offset_address[2:0]}; + assign dword_carry_double = dword_carry[3] & bytes_to_transfer[3]; + end + else begin: dword_carry_useless + assign dword_carry=4'h0; + assign dword_carry_double=1'h0; + end +endgenerate +generate + if(DS_DATA_WIDTH>=128) begin: qword_carry_128 + assign qword_carry = {1'b0, bytes_to_transfer[3:0]} + {1'b0, offset_address[3:0]}; + assign qword_carry_double = qword_carry[4] & bytes_to_transfer[4]; + end + else begin: qword_carry_useless + assign qword_carry=5'h0; + assign qword_carry_double=1'h0; + end +endgenerate +generate + if(DS_DATA_WIDTH>=256) begin: oword_carry_256 + assign oword_carry = {1'b0, bytes_to_transfer[4:0]} + {1'b0, offset_address[4:0]}; + assign oword_carry_double = oword_carry[5] & bytes_to_transfer[5]; + end + else begin: oword_carry_useless + assign oword_carry=6'h0; + assign oword_carry_double=1'h0; + end +endgenerate + assign bytes_lt_one_byte = ~|bytes_to_transfer; + assign bytes_lt_two_byte = ~|bytes_to_transfer[TOTAL_BYTES_WIDTH-1:1]; + assign bytes_lt_two_half = ~|bytes_to_transfer[TOTAL_BYTES_WIDTH-1:1] & ~half_carry; + assign bytes_lt_four_half = ~|bytes_to_transfer[TOTAL_BYTES_WIDTH-1:2] & ~half_carry_double; + assign bytes_lt_four_word = ~|bytes_to_transfer[TOTAL_BYTES_WIDTH-1:2] & ~word_carry[2]; + assign bytes_lt_eight_word = ~|bytes_to_transfer[TOTAL_BYTES_WIDTH-1:3] & ~word_carry_double; + assign bytes_lt_eight_dword = ~|bytes_to_transfer[TOTAL_BYTES_WIDTH-1:3] & ~dword_carry[3]; + assign bytes_lt_sixt_dword = ~|bytes_to_transfer[TOTAL_BYTES_WIDTH-1:4] & ~dword_carry_double; + assign bytes_lt_sixt_qword = ~|bytes_to_transfer[TOTAL_BYTES_WIDTH-1:4] & ~qword_carry[4]; + assign bytes_lt_ttwo_qword = ~|bytes_to_transfer[TOTAL_BYTES_WIDTH-1:5] & ~qword_carry_double; + assign bytes_lt_ttwo_oword = ~|bytes_to_transfer[TOTAL_BYTES_WIDTH-1:5] & ~oword_carry[5]; + assign bytes_lt_sfour_oword = ~|bytes_to_transfer[TOTAL_BYTES_WIDTH-1:6] & ~oword_carry_double; + always @(*) + begin : size_lookup + incrsize = DS_ADDR_AL_WIDTH; + if ((bytes_lt_one_byte || (bytes_lt_two_byte && (&offset_address[DS_ADDR_AL_WIDTH-1:0])))&&(DS_DATA_WIDTH>=16)) begin + incrsize = `AXI_ASIZE_8; + end else if ((bytes_lt_two_half || (bytes_lt_four_half && (&offset_address[DS_ADDR_AL_WIDTH-1:((DS_ADDR_AL_WIDTH>=2) ? 1:0)])))&&(DS_DATA_WIDTH>=32)) begin + incrsize = `AXI_ASIZE_16; + end else if ((bytes_lt_four_word || (bytes_lt_eight_word && (&offset_address[DS_ADDR_AL_WIDTH-1:((DS_ADDR_AL_WIDTH>=3) ? 2:0)])))&&(DS_DATA_WIDTH>=64)) begin + incrsize = `AXI_ASIZE_32; + end else if ((bytes_lt_eight_dword || (bytes_lt_sixt_dword && (&offset_address[DS_ADDR_AL_WIDTH-1:((DS_ADDR_AL_WIDTH>=4) ? 3:0)])))&&(DS_DATA_WIDTH>=128)) begin + incrsize = `AXI_ASIZE_64; + end else if ((bytes_lt_sixt_qword || (bytes_lt_ttwo_qword && (&offset_address[DS_ADDR_AL_WIDTH-1:((DS_ADDR_AL_WIDTH>=5) ? 4:0)])))&&(DS_DATA_WIDTH>=256)) begin + incrsize = `AXI_ASIZE_128; + end else if ((bytes_lt_ttwo_oword || (bytes_lt_sfour_oword && (&offset_address[DS_ADDR_AL_WIDTH-1:((DS_ADDR_AL_WIDTH>=6) ? 5:0)])))&&(DS_DATA_WIDTH>=512)) begin + incrsize = `AXI_ASIZE_256; + end + end + assign final_address = {1'b0, offset_address} + {1'b0, bytes_to_transfer_large[DS_ADDR_AL_WIDTH-1:0]}; + assign overflow = final_address[DS_ADDR_AL_WIDTH]; + assign bytes_to_transfer_large = {8'h0, bytes_to_transfer}; + assign incrlenmaxsize = bytes_to_transfer_large[DS_ADDR_AL_WIDTH+:((DS_AXI3==1) ? 4 : 8)] + 4'b1; + assign incrlen = (overflow) ? incrlenmaxsize : ((DS_AXI3==1) ? {4'b0000,bytes_to_transfer_large[DS_ADDR_AL_WIDTH+:4]} : bytes_to_transfer_large[DS_ADDR_AL_WIDTH+:8]); + +endmodule +`include "Axi_undefs.v"
diff --git a/axi2sramcrs/rtl/upsizer/upsize_rd_cam_slice.v b/axi2sramcrs/rtl/upsizer/upsize_rd_cam_slice.v new file mode 100644 index 0000000..4656541 --- /dev/null +++ b/axi2sramcrs/rtl/upsizer/upsize_rd_cam_slice.v
@@ -0,0 +1,263 @@ +//**************************************************************************** +// +// Copyright 2017-2023 Vivante Corporation +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +//**************************************************************************** +// Auto-generated file on 11/03/2023. +// +//**************************************************************************** + +module upsize_rd_cam_slice + ( + aresetn, + aclk, + match_id, + store, + push_slice, + pop_slice, + update, + match_pointer, + hazard_in, + hazard_pointer, + archannel_data, + rlast_in, + hazard, + match, + addr_out, + last_addr_match, + valid, + beat_complete, + rdata_byte_mask + ); +`include "Axi.v" +parameter ARID_WIDTH=4; +parameter US_DATA_WIDTH=128; +parameter DS_DATA_WIDTH=256; +parameter RD_ISS=8; +parameter ARCHAN_WIDTH=20; +localparam DS_WSTRB_WIDTH=DS_DATA_WIDTH/8; +localparam US_WSTRB_WIDTH=US_DATA_WIDTH/8; +localparam DS_ADDR_AL_WIDTH=$clog2(DS_WSTRB_WIDTH); +localparam US_ADDR_AL_WIDTH=$clog2(US_WSTRB_WIDTH); +localparam PTR_WIDTH=$clog2(RD_ISS+1); +localparam UPSIZE_WIDTH=DS_ADDR_AL_WIDTH-US_ADDR_AL_WIDTH; + input aresetn; + input aclk; + input [ARID_WIDTH-1:0] match_id; + input store; + input push_slice; + input pop_slice; + input update; + input [PTR_WIDTH-1:0] hazard_pointer; + input [PTR_WIDTH-1:0] match_pointer; + input hazard_in; + input [ARCHAN_WIDTH-1:0] archannel_data; + input rlast_in; + wire wrap_fits; + output hazard; + output valid; + output match; + output [UPSIZE_WIDTH-1:0] addr_out; + output last_addr_match; + output beat_complete; + output [US_WSTRB_WIDTH-1:0] rdata_byte_mask; + reg [ARID_WIDTH-1:0] id_reg; + reg [PTR_WIDTH-1:0] pointer_reg; + reg hazard_reg; + reg valid_reg; + reg last_reg; + reg n_response_reg; + reg wrap_fits_reg; + reg [DS_ADDR_AL_WIDTH-1:0] addr_reg; + reg [DS_ADDR_AL_WIDTH-1:0] addr_mask_reg; + reg [DS_ADDR_AL_WIDTH-1:0] addr_mask_end_reg; + reg [2:0] size_reg; + reg bypass_reg; + reg [DS_ADDR_AL_WIDTH-1:0] addr_next; + reg [7:0] size_incr; + wire [ARID_WIDTH-1:0] next_id_reg; + wire [PTR_WIDTH-1:0] next_pointer_reg; + wire next_hazard_reg; + wire next_valid_reg; + wire next_last_reg; + wire next_n_response_reg; + wire [DS_ADDR_AL_WIDTH-1:0] next_addr_reg; + wire allowed_to_match; + wire rid_match; + wire arid_match; + wire pointer_match; + wire match_i; + wire last_reg_wr_en; + wire hazard_reg_wr_en; + wire valid_reg_wr_en; + wire n_response_reg_wr_en; + wire default_reg_wr_en; + wire addr_reg_wr; + wire [2:0] size_in; + wire n_response; + wire bypass_in; + wire [DS_ADDR_AL_WIDTH-1:0] addr; + wire [DS_ADDR_AL_WIDTH-1:0] addr_mask; + wire [DS_ADDR_AL_WIDTH-1:0] addr_mask_end; + wire [ARID_WIDTH-1:0] hazard_id; + wire boundary_cross; + wire [DS_ADDR_AL_WIDTH:0] addr_incr; + wire can_complete; + wire last_addr_match_int; + wire beat_complete_i; +assign { + wrap_fits, + n_response, + hazard_id, + addr_mask_end, + addr_mask, + addr, + bypass_in, + size_in + } = archannel_data; + assign rid_match = (match_id == id_reg); + assign arid_match = (hazard_id == id_reg); + assign allowed_to_match = valid_reg && ~hazard_reg; + assign match_i = allowed_to_match && rid_match; + assign match = match_i; + assign can_complete = match_i && ~|n_response_reg; + reg [63:0] size_mask_r; + wire [US_WSTRB_WIDTH-1:0] size_mask,byte_mask,byte_mask_r; + wire [US_WSTRB_WIDTH-1:0] rdata_byte_mask ; + assign rdata_byte_mask = byte_mask & {US_WSTRB_WIDTH{match_i}}; + always @(size_reg) + begin : size_mask_p + case (size_reg) + 3'b000 : size_mask_r = {64'b00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000001}; + 3'b001 : size_mask_r = {64'b00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000011}; + 3'b010 : size_mask_r = {64'b00000000_00000000_00000000_00000000_00000000_00000000_00000000_00001111}; + 3'b011 : size_mask_r = {64'b00000000_00000000_00000000_00000000_00000000_00000000_00000000_11111111}; + 3'b100 : size_mask_r = {64'b00000000_00000000_00000000_00000000_00000000_00000000_11111111_11111111}; + 3'b101 : size_mask_r = {64'b00000000_00000000_00000000_00000000_11111111_11111111_11111111_11111111}; + 3'b110 : size_mask_r = {64'b00000000_00000000_11111111_11111111_11111111_11111111_11111111_11111111}; + 3'b111 : size_mask_r = {64'b11111111_11111111_11111111_11111111_11111111_11111111_11111111_11111111}; + default : size_mask_r = {64'bx}; + endcase + end +assign size_mask = size_mask_r[US_WSTRB_WIDTH-1:0] ; +assign byte_mask_r = (size_mask << addr_reg[US_ADDR_AL_WIDTH-1:0]) ;//& { {(US_WSTRB_WIDTH-addr_reg){1'b1}}, {addr_reg{1'b0}}}; +assign byte_mask = byte_mask_r[US_WSTRB_WIDTH-1:0] ; + assign hazard = arid_match && last_reg && valid_reg && ~(can_complete && pop_slice); + assign default_reg_wr_en = (store && push_slice); + assign next_id_reg = hazard_id; + always @(posedge aclk) + begin : id_seq + if (default_reg_wr_en) + id_reg <= next_id_reg; + end + assign next_pointer_reg = hazard_pointer; + always @(posedge aclk) + begin : pointer_seq + if (default_reg_wr_en) + pointer_reg <= next_pointer_reg; + end + assign next_last_reg = (store) ? 1'b1 : + ((arid_match) ? 1'b0 : last_reg); + assign last_reg_wr_en = (default_reg_wr_en || (arid_match && valid_reg && push_slice)); + always @(posedge aclk) + begin : last_seq + if (last_reg_wr_en) + last_reg <= next_last_reg; + end + assign pointer_match = (pointer_reg == match_pointer); + assign next_hazard_reg = (store) ? hazard_in : 1'b0; + assign hazard_reg_wr_en = (default_reg_wr_en || (pointer_match && valid_reg && pop_slice && rid_match)); + always @(posedge aclk) + begin : hazard_seq + if (hazard_reg_wr_en) + hazard_reg <= next_hazard_reg; + end + assign next_valid_reg = (store && push_slice) || (n_response_reg); + assign valid_reg_wr_en = default_reg_wr_en || (match_i && pop_slice); + always @(posedge aclk or negedge aresetn) + begin : valid_seq + if (!aresetn) + valid_reg <= 1'b0; + else if (valid_reg_wr_en) + valid_reg <= next_valid_reg; + end + assign valid = valid_reg; + assign next_n_response_reg = (store && push_slice) ? n_response : (n_response_reg - 1'b1); + assign n_response_reg_wr_en = (rid_match && ~hazard_reg && rlast_in && update && beat_complete_i) || default_reg_wr_en; + always @(posedge aclk or negedge aresetn) + begin : two_resp_seq + if (!aresetn) + n_response_reg <= {1{1'b0}}; + else if (n_response_reg_wr_en) + n_response_reg <= next_n_response_reg; + end + assign boundary_cross = |((addr_incr ^ {1'b0, addr_reg}) & {1'b1, ~addr_mask_reg}) & ~wrap_fits_reg; + always @(*) + begin : size_incr_p + case (size_reg) + `AXI_ASIZE_8 : size_incr = {7'b0, 1'b1}; + `AXI_ASIZE_16 : size_incr = {6'b0, 2'b10}; + `AXI_ASIZE_32 : size_incr = {5'b0, 3'b100}; + `AXI_ASIZE_64 : size_incr = {4'b0, 4'b1000}; + `AXI_ASIZE_128 : size_incr = {3'b0, 5'b10000}; + `AXI_ASIZE_256 : size_incr = {2'b0, 6'b100000}; + `AXI_ASIZE_512 : size_incr = {1'b0, 7'b1000000}; + default : size_incr = {8'bx}; + endcase + end + assign addr_incr = {1'b0, addr_reg} + size_incr[DS_ADDR_AL_WIDTH:0]; + always @(*) + begin : addr_reg_nxt_p + integer index_i; + for (index_i = 0; index_i < DS_ADDR_AL_WIDTH ; index_i = index_i + 1) + begin + if ( addr_mask_reg[index_i] == 1'b1) + addr_next[index_i] = addr_incr[index_i]; + else + addr_next[index_i] = addr_reg[index_i]; + end + end + assign addr_reg_wr = default_reg_wr_en || (match_i && update); + assign next_addr_reg = (store && push_slice) ? addr : addr_next; + always @(posedge aclk or negedge aresetn) + begin : addr_seq + if (!aresetn) + addr_reg <= {DS_ADDR_AL_WIDTH{1'b0}}; + else if (addr_reg_wr) + addr_reg <= next_addr_reg; + end + assign addr_out = addr_reg[DS_ADDR_AL_WIDTH-1:US_ADDR_AL_WIDTH] & {UPSIZE_WIDTH{match_i}}; + assign last_addr_match_int = (((addr_reg & addr_mask_reg) == (addr_mask_end_reg & addr_mask_reg)) || bypass_reg) && ~|n_response_reg; + assign last_addr_match = last_addr_match_int; + assign beat_complete_i = boundary_cross || bypass_reg; + assign beat_complete = beat_complete_i; + always @(posedge aclk or negedge aresetn) + begin : ardata_seq + if (!aresetn) begin + addr_mask_reg <= {DS_ADDR_AL_WIDTH{1'b0}}; + addr_mask_end_reg <= {DS_ADDR_AL_WIDTH{1'b0}}; + size_reg <= 3'b0; + bypass_reg <= 1'b0; + wrap_fits_reg <= 1'b0; + end else if (default_reg_wr_en) begin + addr_mask_reg <= addr_mask; + addr_mask_end_reg <= addr_mask_end; + size_reg <= size_in; + bypass_reg <= bypass_in; + wrap_fits_reg <= wrap_fits; + end + end +endmodule +`include "Axi_undefs.v"
diff --git a/axi2sramcrs/rtl/upsizer/upsize_rd_chan.v b/axi2sramcrs/rtl/upsizer/upsize_rd_chan.v new file mode 100644 index 0000000..debc58c --- /dev/null +++ b/axi2sramcrs/rtl/upsizer/upsize_rd_chan.v
@@ -0,0 +1,280 @@ +//**************************************************************************** +// +// Copyright 2017-2023 Vivante Corporation +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +//**************************************************************************** +// Auto-generated file on 11/03/2023. +// +//**************************************************************************** + +module upsize_rd_chan + ( + archannel_ready, rready_m, rvalid_s, rdata_s, rid_s, rresp_s, + rlast_s, ruser_s, + aclk, aresetn, archannel_valid, archannel_data, rvalid_m, rdata_m, + rid_m, rresp_m, rlast_m, ruser_m, rready_s + ); +parameter ARID_WIDTH=4; +parameter AWID_WIDTH=4; +parameter ADDR_WIDTH=32; +parameter US_DATA_WIDTH=128; +parameter DS_DATA_WIDTH=256; +parameter USER_WIDTH=4; +parameter RD_ISS=8; +localparam DS_WSTRB_WIDTH=DS_DATA_WIDTH/8; +localparam US_WSTRB_WIDTH=US_DATA_WIDTH/8; +localparam DS_ADDR_AL_WIDTH=$clog2(DS_WSTRB_WIDTH); +localparam US_ADDR_AL_WIDTH=$clog2(US_WSTRB_WIDTH); +localparam ARFMT_WIDTH=1+1+ARID_WIDTH+DS_ADDR_AL_WIDTH*3+1+3; +localparam AWFMT_WIDTH=1+US_ADDR_AL_WIDTH*2+3+1; +localparam US_AW_WIDTH=4+USER_WIDTH+AWID_WIDTH+ADDR_WIDTH+8+3+2+2+4+4+3+1; +localparam US_AR_WIDTH=4+USER_WIDTH+ARID_WIDTH+ADDR_WIDTH+8+3+2+2+4+4+3+1; +localparam US_R_WIDTH=USER_WIDTH+ARID_WIDTH+US_DATA_WIDTH+2+1; +localparam US_W_WIDTH=USER_WIDTH+AWID_WIDTH+US_DATA_WIDTH+US_WSTRB_WIDTH+1; +localparam US_B_WIDTH=USER_WIDTH+AWID_WIDTH+2; +localparam PTR_WIDTH=$clog2(RD_ISS+1); +localparam UPSIZE_WIDTH=DS_ADDR_AL_WIDTH-US_ADDR_AL_WIDTH; +localparam DATA_RATIO=(DS_DATA_WIDTH/US_DATA_WIDTH); + input aclk; + input aresetn; + input archannel_valid; + output archannel_ready; + input [ARFMT_WIDTH-1:0] archannel_data; + input rvalid_m; + output rready_m; + input [DS_DATA_WIDTH-1:0] rdata_m; + input [ARID_WIDTH-1:0] rid_m; + input [1:0] rresp_m; + input rlast_m; + input [USER_WIDTH-1:0] ruser_m; + input rready_s; + output rvalid_s; + output [US_DATA_WIDTH-1:0] rdata_s; + output [ARID_WIDTH-1:0] rid_s; + output [1:0] rresp_s; + output rlast_s; + output [USER_WIDTH-1:0] ruser_s; + wire archannel_ready_i; + wire [RD_ISS-1:0] match_bus; + wire [RD_ISS-1:0] hazard_bus; + wire [RD_ISS-1:0] valid_bus; + wire [RD_ISS-1:0] last_addr_match_bus; + wire [RD_ISS-1:0] beat_complete_slice_bus; + wire hazard; + wire last_addr_match; + wire beat_complete_slice; + wire archannel_hndshk; + wire rchannel_hndshk; + wire push_slice; + wire pop_slice; + wire update; + wire beat_complete; + wire [UPSIZE_WIDTH-1:0] data_select; + reg [UPSIZE_WIDTH-1:0] addr; + wire [ARID_WIDTH-1:0] rid_m; + wire [DS_DATA_WIDTH-1:0] rdata; + wire rlast_in; + wire rlast_s_i; + wire [1:0] rresp_s; + wire [UPSIZE_WIDTH-1:0] addr_out[RD_ISS-1:0]; + wire [US_WSTRB_WIDTH-1:0] rdata_byte_mask[RD_ISS-1:0]; + wire [RD_ISS-1:0] const_onehot[RD_ISS-1:0]; + wire [RD_ISS-1:0] valid_bus_zero_lsb; + wire [PTR_WIDTH-1:0] hazard_bus_one_pos[RD_ISS-1:0]; + wire [PTR_WIDTH-1:0] match_bus_one_pos[RD_ISS-1:0]; + reg [US_DATA_WIDTH-1:0] rdata_beat_mask; + reg [US_DATA_WIDTH-1:0] rdata_s_demux; + reg [PTR_WIDTH-1:0] hazard_pointer; + reg [PTR_WIDTH-1:0] match_pointer; + reg [RD_ISS-1:0] store; + assign rid_s = rid_m; + assign rlast_in = rlast_m; + assign rresp_s = rresp_m; + assign ruser_s = ruser_m; + assign rdata = rdata_m; + assign hazard = |hazard_bus; + assign last_addr_match = |(last_addr_match_bus & match_bus); + assign beat_complete_slice = |(beat_complete_slice_bus & match_bus); +always @(*) +begin:for_addr + integer i,j; + addr = {UPSIZE_WIDTH{1'h0}}; + for(i=0;i<UPSIZE_WIDTH;i=i+1) + begin: for_addr_i + for(j=0;j<RD_ISS;j=j+1) + begin: for_addr_j + addr[i] = addr[i]|addr_out[j][i]; + end + end +end +reg [US_WSTRB_WIDTH-1:0] rdata_byte_mask_i; +always @(*) +begin:for_rdata_beat + integer i,j; + rdata_beat_mask = {US_DATA_WIDTH{1'b0}}; + for(i=0;i<US_WSTRB_WIDTH;i=i+1) + for(j=0;j<8;j=j+1) + rdata_beat_mask[i*8+j] = rdata_byte_mask_i[i]; +end +always @(*) +begin:for_rdata_byte + integer i,j; + rdata_byte_mask_i = {US_WSTRB_WIDTH{1'b0}}; + for(i=0;i<US_WSTRB_WIDTH;i=i+1) + for(j=0;j<RD_ISS;j=j+1) + begin + rdata_byte_mask_i[i] = rdata_byte_mask_i[i] | rdata_byte_mask[j][i] ; + end +end + assign data_select = addr; +/* +always@(*) +begin:rdata_s_demux_a + integer i; + for(i=0;i<DATA_RATIO;i=i+1) + begin + if(data_select == i) + begin + rdata_s_demux = rdata[US_DATA_WIDTH*i+:US_DATA_WIDTH];//[(US_DATA_WIDTH*(i+1)-1):US_DATA_WIDTH*i]; + end + end +end +*/ +generate + if(DATA_RATIO==2) + begin:demux_D2 + always@(*) + begin + case(data_select) + 0:rdata_s_demux=rdata[US_DATA_WIDTH-1:0]; + 1:rdata_s_demux=rdata[US_DATA_WIDTH*2-1:US_DATA_WIDTH]; + default:rdata_s_demux= {US_DATA_WIDTH{1'b0}}; + endcase + end + end + else if(DATA_RATIO==4) + begin:demux_D4 + always@(*) + begin + case(data_select) + 0:rdata_s_demux=rdata[US_DATA_WIDTH-1:0]; + 1:rdata_s_demux=rdata[US_DATA_WIDTH*2-1:US_DATA_WIDTH]; + 2:rdata_s_demux=rdata[US_DATA_WIDTH*3-1:US_DATA_WIDTH*2]; + 3:rdata_s_demux=rdata[US_DATA_WIDTH*4-1:US_DATA_WIDTH*3]; + default:rdata_s_demux={US_DATA_WIDTH{1'b0}}; + endcase + end + end + else if(DATA_RATIO==8) + begin:demux_D8 + always@(*) + begin + case(data_select) + 0:rdata_s_demux=rdata[US_DATA_WIDTH-1:0]; + 1:rdata_s_demux=rdata[US_DATA_WIDTH*2-1:US_DATA_WIDTH]; + 2:rdata_s_demux=rdata[US_DATA_WIDTH*3-1:US_DATA_WIDTH*2]; + 3:rdata_s_demux=rdata[US_DATA_WIDTH*4-1:US_DATA_WIDTH*3]; + 4:rdata_s_demux=rdata[US_DATA_WIDTH*5-1:US_DATA_WIDTH*4]; + 5:rdata_s_demux=rdata[US_DATA_WIDTH*6-1:US_DATA_WIDTH*5]; + 6:rdata_s_demux=rdata[US_DATA_WIDTH*7-1:US_DATA_WIDTH*6]; + 7:rdata_s_demux=rdata[US_DATA_WIDTH*8-1:US_DATA_WIDTH*7]; + default:rdata_s_demux={US_DATA_WIDTH{1'b0}}; + endcase + end + end +endgenerate +assign rdata_s = rdata_s_demux & rdata_beat_mask; + assign rlast_s_i = last_addr_match && rlast_in; + assign rlast_s = rlast_s_i; + assign archannel_ready_i = ~&valid_bus; + assign archannel_ready = archannel_ready_i; + assign archannel_hndshk = archannel_ready_i && archannel_valid; + assign push_slice = archannel_hndshk; +genvar i; +generate + for(i=0;i<RD_ISS;i=i+1) begin:const_onehot_g + if(RD_ISS==1) begin: rd_iss_1 + assign const_onehot[i]=(1'h1<<i); + end + else begin: rd_iss_n + assign const_onehot[i]=({{(RD_ISS-1){1'h0}},1'h1}<<i); + end + assign valid_bus_zero_lsb[i]=((~valid_bus[i:0])==const_onehot[i][i:0]); + assign hazard_bus_one_pos[i]={PTR_WIDTH{hazard_bus[i]}}&i; + assign match_bus_one_pos[i]={PTR_WIDTH{match_bus[i]}}&i; + always @(*) + begin : store_decode + if (&valid_bus) + store[i] = match_bus[i]; + else + store[i] = valid_bus_zero_lsb[i]; + end + end +endgenerate + always @(*) + begin : hazard_num_distibution + integer a; + hazard_pointer={PTR_WIDTH{1'h0}}; + for(a=0;a<RD_ISS;a=a+1) begin + hazard_pointer=hazard_pointer | hazard_bus_one_pos[a]; + end + end + always @(*) + begin : match_num_distibution + integer a; + match_pointer={PTR_WIDTH{1'h0}}; + for(a=0;a<RD_ISS;a=a+1) begin + match_pointer=match_pointer | match_bus_one_pos[a]; + end + end + assign beat_complete = (rlast_s_i | beat_complete_slice) && update; + assign rready_m = beat_complete && rvalid_m; + assign rvalid_s = rvalid_m; + assign rchannel_hndshk = rvalid_s && rready_s; + assign update = rchannel_hndshk; + assign pop_slice = update && rlast_s_i; +generate +for(i=0;i<RD_ISS;i=i+1) begin: rd_cam_slice_inst + upsize_rd_cam_slice #( + .ARID_WIDTH(ARID_WIDTH), + .US_DATA_WIDTH(US_DATA_WIDTH), + .DS_DATA_WIDTH(DS_DATA_WIDTH), + .RD_ISS(RD_ISS), + .ARCHAN_WIDTH(ARFMT_WIDTH) + ) u_upsize_rd_cam_slice + ( + .aresetn (aresetn), + .aclk (aclk), + .match_id (rid_m), + .store (store[i]), + .push_slice (push_slice), + .pop_slice (pop_slice), + .update (update), + .match_pointer (match_pointer), + .archannel_data (archannel_data), + .rlast_in (rlast_in), + .hazard_in (hazard), + .hazard_pointer (hazard_pointer), + .hazard (hazard_bus[i]), + .match (match_bus[i]), + .valid (valid_bus[i]), + .addr_out (addr_out[i]), + .last_addr_match (last_addr_match_bus[i]), + .beat_complete (beat_complete_slice_bus[i]), + .rdata_byte_mask (rdata_byte_mask[i]) + ); +end +endgenerate +endmodule
diff --git a/axi2sramcrs/rtl/upsizer/upsize_resp_cam_slice.v b/axi2sramcrs/rtl/upsizer/upsize_resp_cam_slice.v new file mode 100644 index 0000000..0f0a899 --- /dev/null +++ b/axi2sramcrs/rtl/upsizer/upsize_resp_cam_slice.v
@@ -0,0 +1,145 @@ +//**************************************************************************** +// +// Copyright 2017-2023 Vivante Corporation +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +//**************************************************************************** +// Auto-generated file on 11/03/2023. +// +//**************************************************************************** + +module upsize_resp_cam_slice + ( + aresetn, + aclk, + matchid, + hazardid, + store, + push_slice, + pop_slice, + update, + match_pointer, + hazard_in, + hazard_pointer, + n_response, + bresp_in, + hazard, + match, + valid, + bresp_out + ); +parameter ID_WIDTH=4; +parameter USER_WIDTH=4; +parameter PTR_WIDTH=8; + input aresetn; + input aclk; + input [ID_WIDTH-1:0] matchid; + input [ID_WIDTH-1:0] hazardid; + input store; + input push_slice; + input pop_slice; + input update; + input [PTR_WIDTH-1:0] hazard_pointer; + input [PTR_WIDTH-1:0] match_pointer; + input hazard_in; + input n_response; + input [1:0] bresp_in; + output hazard; + output match; + output valid; + output [1:0] bresp_out; + reg [ID_WIDTH-1:0] id_reg; + reg [PTR_WIDTH-1:0] pointer_reg; + reg hazard_reg; + reg valid_reg; + reg last_reg; + reg n_response_reg; + reg [1:0] bresp_reg; + wire [ID_WIDTH-1:0] next_id_reg; + wire [PTR_WIDTH-1:0] next_pointer_reg; + wire next_hazard_reg; + wire next_valid_reg; + wire next_last_reg; + wire next_n_response_reg; + wire [1:0] next_bresp_reg; + wire allowed_to_match; + wire bid_match; + wire awid_match; + wire match_i; + wire last_reg_wr_en; + wire hazard_reg_wr_en; + wire valid_reg_wr_en; + wire n_response_reg_wr_en; + wire default_reg_wr_en; + wire pointer_match; + assign bid_match = (matchid == id_reg); + assign awid_match = (hazardid == id_reg); + assign allowed_to_match = valid_reg && ~hazard_reg && ~n_response_reg; + assign match_i = allowed_to_match && bid_match; + assign match = match_i; + assign hazard = awid_match && last_reg && valid_reg && ~(match_i && pop_slice); + assign default_reg_wr_en = (store && push_slice); + assign next_id_reg = hazardid; + always @(posedge aclk) + begin : id_seq + if (default_reg_wr_en) + id_reg <= next_id_reg; + end + assign next_pointer_reg = hazard_pointer; + always @(posedge aclk) + begin : pointer_seq + if (default_reg_wr_en) + pointer_reg <= next_pointer_reg; + end + assign next_last_reg = (store && push_slice) ? 1'b1 : + ((awid_match) ? 1'b0 : last_reg); + assign last_reg_wr_en = (default_reg_wr_en || (awid_match && valid_reg && push_slice)); + always @(posedge aclk) + begin : last_seq + if (last_reg_wr_en) + last_reg <= next_last_reg; + end + assign pointer_match = (pointer_reg == match_pointer); + assign next_hazard_reg = (store && push_slice) ? hazard_in : 1'b0; + assign hazard_reg_wr_en = (default_reg_wr_en || (pointer_match && valid_reg && pop_slice)); + always @(posedge aclk) + begin : hazard_seq + if (hazard_reg_wr_en) + hazard_reg <= next_hazard_reg; + end + assign next_valid_reg = (store && push_slice) || (n_response_reg); + assign valid_reg_wr_en = default_reg_wr_en || (match_i && pop_slice); + always @(posedge aclk or negedge aresetn) + begin : valid_seq + if (!aresetn) + valid_reg <= 1'b0; + else if (valid_reg_wr_en) + valid_reg <= next_valid_reg; + end + assign valid = valid_reg; + assign next_n_response_reg = (store && push_slice) ? n_response : 1'b0; + assign next_bresp_reg = (store && push_slice) ? 2'b0 : (bresp_in | bresp_reg); + assign n_response_reg_wr_en = (bid_match && ~hazard_reg && update && (n_response_reg)) || (store && push_slice); + always @(posedge aclk or negedge aresetn) + begin : two_resp_seq + if (!aresetn) begin + n_response_reg <= 1'b0; + bresp_reg <= 2'b0; + end else if (n_response_reg_wr_en) begin + n_response_reg <= next_n_response_reg; + bresp_reg <= next_bresp_reg; + end + end + assign bresp_out = {2{match_i}} & bresp_reg; +endmodule
diff --git a/axi2sramcrs/rtl/upsizer/upsize_slave_domain.v b/axi2sramcrs/rtl/upsizer/upsize_slave_domain.v new file mode 100644 index 0000000..b9a9799 --- /dev/null +++ b/axi2sramcrs/rtl/upsizer/upsize_slave_domain.v
@@ -0,0 +1,754 @@ +//**************************************************************************** +// +// Copyright 2017-2023 Vivante Corporation +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +//**************************************************************************** +// Auto-generated file on 11/03/2023. +// +//**************************************************************************** + +`include "Axi.v" +module upsize_slave_domain + ( + awready_s, wready_s, bid_s, bresp_s, bvalid_s, buser_s, arready_s, + rid_s, rdata_s, rresp_s, rlast_s, rvalid_s, ruser_s, aw_data, + aw_valid, b_ready, ar_data, ar_valid, r_ready, w_data, w_valid, + awid_s, awaddr_s, awlen_s, awsize_s, awburst_s, awlock_s, + awcache_s, awprot_s, awvalid_s, awvalid_vect_s, awuser_s, + awregion_s, wdata_s, wstrb_s, wlast_s, wvalid_s, wid_s, wuser_s, + bready_s, arid_s, araddr_s, arlen_s, arsize_s, arburst_s, arlock_s, + arcache_s, arprot_s, arvalid_s, arvalid_vect_s, aruser_s, + arregion_s, rready_s, awqv_s, arqv_s, aw_ready, b_data, b_valid, + ar_ready, r_data, r_valid, w_ready, aclk, aresetn + ); +parameter ARID_WIDTH=4; +parameter AWID_WIDTH=4; +parameter ADDR_WIDTH=32; +parameter US_DATA_WIDTH=128; +parameter DS_DATA_WIDTH=256; +parameter USER_WIDTH=4; +parameter RD_ISS=8; +parameter WR_ISS=8; +parameter DS_AXI3=1'h1; +localparam DS_WSTRB_WIDTH=DS_DATA_WIDTH/8; +localparam US_WSTRB_WIDTH=US_DATA_WIDTH/8; +localparam DS_ADDR_AL_WIDTH=$clog2(DS_WSTRB_WIDTH); +localparam US_ADDR_AL_WIDTH=$clog2(US_WSTRB_WIDTH); +localparam ARFMT_WIDTH=1+1+ARID_WIDTH+DS_ADDR_AL_WIDTH*3+1+3; +localparam AWFMT_WIDTH=AWID_WIDTH+1+4+1+DS_ADDR_AL_WIDTH*2+3+1; +localparam US_AW_WIDTH=4+USER_WIDTH+AWID_WIDTH+ADDR_WIDTH+8+3+2+2+4+4+3+1; +localparam US_AR_WIDTH=4+USER_WIDTH+ARID_WIDTH+ADDR_WIDTH+8+3+2+2+4+4+3+1; +localparam US_R_WIDTH=USER_WIDTH+ARID_WIDTH+US_DATA_WIDTH+2+1; +localparam US_W_WIDTH=USER_WIDTH+AWID_WIDTH+US_DATA_WIDTH+US_WSTRB_WIDTH+1; +localparam US_B_WIDTH=USER_WIDTH+AWID_WIDTH+2; +localparam AW_IDB_WIDTH=US_AW_WIDTH; +localparam AR_IDB_WIDTH=US_AR_WIDTH; +localparam W_IDB_WIDTH=AWID_WIDTH+USER_WIDTH+DS_DATA_WIDTH+DS_WSTRB_WIDTH+1; +localparam R_IDB_WIDTH=USER_WIDTH+ARID_WIDTH+DS_DATA_WIDTH+2+1; +localparam B_IDB_WIDTH=USER_WIDTH+2+AWID_WIDTH; +localparam DATA_RATIO=(DS_DATA_WIDTH/US_DATA_WIDTH); +localparam BCHAN_WIDTH=AWID_WIDTH+1; + input [AWID_WIDTH-1:0] awid_s; + input [ADDR_WIDTH-1:0] awaddr_s; + input [7:0] awlen_s; + input [2:0] awsize_s; + input [1:0] awburst_s; + input [1:0] awlock_s; + input [3:0] awcache_s; + input [2:0] awprot_s; + input awvalid_s; + input awvalid_vect_s; + output awready_s; + input [USER_WIDTH-1:0] awuser_s; + input [3:0] awregion_s; + input [US_DATA_WIDTH-1:0] wdata_s; + input [US_WSTRB_WIDTH-1:0] wstrb_s; + input wlast_s; + input wvalid_s; + output wready_s; + input [AWID_WIDTH-1:0] wid_s; + input [USER_WIDTH-1:0] wuser_s; + output [AWID_WIDTH-1:0] bid_s; + output [1:0] bresp_s; + output bvalid_s; + input bready_s; + output [USER_WIDTH-1:0] buser_s; + input [ARID_WIDTH-1:0] arid_s; + input [ADDR_WIDTH-1:0] araddr_s; + input [7:0] arlen_s; + input [2:0] arsize_s; + input [1:0] arburst_s; + input [1:0] arlock_s; + input [3:0] arcache_s; + input [2:0] arprot_s; + input arvalid_s; + input arvalid_vect_s; + output arready_s; + input [USER_WIDTH-1:0] aruser_s; + input [3:0] arregion_s; + output [ARID_WIDTH-1:0] rid_s; + output [US_DATA_WIDTH-1:0] rdata_s; + output [1:0] rresp_s; + output rlast_s; + output rvalid_s; + input rready_s; + output [USER_WIDTH-1:0] ruser_s; + input [3:0] awqv_s; + input [3:0] arqv_s; + output [AW_IDB_WIDTH-1:0] aw_data; + output aw_valid; + input aw_ready; + input [B_IDB_WIDTH-1:0] b_data; + input b_valid; + output b_ready; + output [AR_IDB_WIDTH-1:0] ar_data; + output ar_valid; + input ar_ready; + input [R_IDB_WIDTH-1:0] r_data; + input r_valid; + output r_ready; + output [W_IDB_WIDTH-1:0] w_data; + output w_valid; + input w_ready; + input aclk; + input aresetn; + wire [W_IDB_WIDTH-1:0] w_boundary_src_data; + wire [W_IDB_WIDTH-1:0] w_boundary_dst_data; + wire w_boundary_dst_valid; + wire w_boundary_dst_ready; + wire w_boundary_src_valid; + wire w_boundary_src_ready; + wire [US_AW_WIDTH-1:0] aw_slave_port_src_data; + wire [US_AW_WIDTH-1:0] aw_slave_port_dst_data; + wire aw_slave_port_dst_valid; + wire aw_slave_port_dst_ready; + wire aw_slave_port_src_valid; + wire aw_slave_port_src_ready; + wire [US_AR_WIDTH-1:0] ar_slave_port_src_data; + wire [US_AR_WIDTH-1:0] ar_slave_port_dst_data; + wire ar_slave_port_dst_valid; + wire ar_slave_port_dst_ready; + wire ar_slave_port_src_valid; + wire ar_slave_port_src_ready; + wire [US_R_WIDTH-1:0] r_slave_port_src_data; + wire [US_R_WIDTH-1:0] r_slave_port_dst_data; + wire [US_W_WIDTH-1:0] w_slave_port_src_data; + wire [US_W_WIDTH-1:0] w_slave_port_dst_data; + wire [US_B_WIDTH-1:0] b_slave_port_src_data; + wire [US_B_WIDTH-1:0] b_slave_port_dst_data; + wire [BCHAN_WIDTH-1:0] bdata_data; + wire bdata_valid; + wire bdata_ready; + wire [AWFMT_WIDTH-1:0] awdata_data; + wire awdata_valid; + wire awdata_ready; + wire merge; + wire merge_clear; + wire [DATA_RATIO-1:0] data_select; + wire strb_skid_valid; + wire [DS_DATA_WIDTH-1:0] wdata_merged; + wire [DS_WSTRB_WIDTH-1:0] wstrb_merged; + wire [ARFMT_WIDTH-1:0] arfifo_data; + wire arfifo_valid; + wire arfifo_ready; + wire [US_AW_WIDTH-1:0] aw_fmt_src_data; + wire [US_AR_WIDTH-1:0] ar_fmt_src_data; + wire [US_AW_WIDTH-1:0] aw_fmt_dst_data; + wire [US_AR_WIDTH-1:0] ar_fmt_dst_data; + wire [USER_WIDTH-1:0] awuser_bif; + wire [3:0] awregion_bif; + wire [AWID_WIDTH-1:0] awid_bif; + wire [ADDR_WIDTH-1:0] awaddr_bif; + wire [7:0] awlen_bif; + wire [2:0] awsize_bif; + wire [1:0] awburst_bif; + wire [1:0] awlock_bif; + wire [3:0] awcache_bif; + wire [2:0] awprot_bif; + wire awvalid_bif; + wire awvalid_vect_bif; + wire awready_bif; + wire [3:0] awqv_bif; + wire [USER_WIDTH-1:0] aruser_bif; + wire [3:0] arregion_bif; + wire [ARID_WIDTH-1:0] arid_bif; + wire [ADDR_WIDTH-1:0] araddr_bif; + wire [7:0] arlen_bif; + wire [2:0] arsize_bif; + wire [1:0] arburst_bif; + wire [1:0] arlock_bif; + wire [3:0] arcache_bif; + wire [2:0] arprot_bif; + wire arvalid_bif; + wire arvalid_vect_bif; + wire arready_bif; + wire [3:0] arqv_bif; + wire lock_seq; + wire ar_lock_hndshk; + wire ar_unlock_hndshk; + wire [USER_WIDTH-1:0] wuser_bif; + wire [AWID_WIDTH-1:0] wid_bif; + wire wvalid_bif; + wire wready_bif; + wire [DS_DATA_WIDTH-1:0] wdata_bif; + wire [DS_WSTRB_WIDTH-1:0] wstrb_bif; + wire wlast_bif; + wire [USER_WIDTH-1:0] buser_bif; + wire [AWID_WIDTH-1:0] bid_bif; + wire [1:0] bresp_bif; + wire bvalid_bif; + wire bready_bif; + wire [USER_WIDTH-1:0] ruser_bif; + wire [ARID_WIDTH-1:0] rid_bif; + wire [1:0] rresp_bif; + wire [DS_DATA_WIDTH-1:0] rdata_bif; + wire rlast_bif; + wire rvalid_bif; + wire rready_bif; + wire [USER_WIDTH-1:0] aruser_fmt; + wire [3:0] arregion_fmt; + wire arvalid_fmt; + wire arvalid_vect_fmt; + wire [ADDR_WIDTH-1:0] araddr_fmt; + wire [7:0] arlen_fmt; + wire [2:0] arsize_fmt; + wire [1:0] arburst_fmt; + wire [1:0] arlock_fmt; + wire [3:0] arcache_fmt; + wire [2:0] arprot_fmt; + wire [ARID_WIDTH-1:0] arid_fmt; + wire arready_fmt; + wire [3:0] arqv_fmt; + wire [USER_WIDTH-1:0] awuser_fmt; + wire [3:0] awregion_fmt; + wire awvalid_fmt; + wire awvalid_vect_fmt; + wire [ADDR_WIDTH-1:0] awaddr_fmt; + wire [7:0] awlen_fmt; + wire [2:0] awsize_fmt; + wire [1:0] awburst_fmt; + wire [1:0] awlock_fmt; + wire [3:0] awcache_fmt; + wire [2:0] awprot_fmt; + wire [AWID_WIDTH-1:0] awid_fmt; + wire awready_fmt; + wire [3:0] awqv_fmt; + wire [USER_WIDTH-1:0] aruser_axi_r; + wire [3:0] arregion_axi_r; + wire arvalid_axi_r; + wire arvalid_vect_axi_r; + wire [ADDR_WIDTH-1:0] araddr_axi_r; + wire [7:0] arlen_axi_r; + wire [2:0] arsize_axi_r; + wire [1:0] arburst_axi_r; + wire [1:0] arlock_axi_r; + wire [3:0] arcache_axi_r; + wire [2:0] arprot_axi_r; + wire [ARID_WIDTH-1:0] arid_axi_r; + wire arready_axi_r; + wire [3:0] arqv_axi_r; + wire [USER_WIDTH-1:0] awuser_axi_r; + wire [3:0] awregion_axi_r; + wire awvalid_axi_r; + wire awvalid_vect_axi_r; + wire [ADDR_WIDTH-1:0] awaddr_axi_r; + wire [7:0] awlen_axi_r; + wire [2:0] awsize_axi_r; + wire [1:0] awburst_axi_r; + wire [1:0] awlock_axi_r; + wire [3:0] awcache_axi_r; + wire [2:0] awprot_axi_r; + wire [AWID_WIDTH-1:0] awid_axi_r; + wire awready_axi_r; + wire [3:0] awqv_axi_r; + wire [USER_WIDTH-1:0] ruser_axi_r; + wire rvalid_axi_r; + wire rlast_axi_r; + wire [US_DATA_WIDTH-1:0] rdata_axi_r; + wire [1:0] rresp_axi_r; + wire [ARID_WIDTH-1:0] rid_axi_r; + wire rready_axi_r; + wire [USER_WIDTH-1:0] wuser_axi_r; + wire [AWID_WIDTH-1:0] wid_axi_r; + wire wvalid_axi_r; + wire wlast_axi_r; + wire [US_DATA_WIDTH-1:0] wdata_axi_r; + wire [US_WSTRB_WIDTH-1:0] wstrb_axi_r; + wire wready_axi_r; + wire [USER_WIDTH-1:0] buser_axi_r; + wire bvalid_axi_r; + wire [1:0] bresp_axi_r; + wire [AWID_WIDTH-1:0] bid_axi_r; + wire bready_axi_r; + assign aw_fmt_src_data = { + awregion_axi_r, + awuser_axi_r, + awid_axi_r, + awaddr_axi_r, + awlen_axi_r, + awsize_axi_r, + awburst_axi_r, + awlock_axi_r, + awcache_axi_r, + awqv_axi_r, + awprot_axi_r, + awvalid_vect_axi_r}; + assign awvalid_fmt = awvalid_axi_r; + assign awready_axi_r = awready_fmt; + assign aw_fmt_dst_data = aw_fmt_src_data; + assign { + awregion_fmt, + awuser_fmt, + awid_fmt, + awaddr_fmt, + awlen_fmt, + awsize_fmt, + awburst_fmt, + awlock_fmt, + awcache_fmt, + awqv_fmt, + awprot_fmt, + awvalid_vect_fmt} = aw_fmt_dst_data; + upsize_wr_addr_fmt #( + .ARID_WIDTH(ARID_WIDTH), + .AWID_WIDTH(AWID_WIDTH), + .ADDR_WIDTH(ADDR_WIDTH), + .US_DATA_WIDTH(US_DATA_WIDTH), + .DS_DATA_WIDTH(DS_DATA_WIDTH), + .USER_WIDTH(USER_WIDTH), + .DS_AXI3(DS_AXI3) + ) u_axi_write_address_format + ( + .aresetn (aresetn), + .aclk (aclk), + .lock_seq (lock_seq), + .ar_lock_hndshk (ar_lock_hndshk), + .ar_unlock_hndshk (ar_unlock_hndshk), + .bdata_data (bdata_data), + .bdata_valid (bdata_valid), + .bdata_ready (bdata_ready), + .awfmt_valid (awdata_valid), + .awfmt_ready (awdata_ready), + .awfmt_data (awdata_data), + .awid_s (awid_fmt), + .awaddr_s (awaddr_fmt), + .awlen_s (awlen_fmt), + .awsize_s (awsize_fmt), + .awburst_s (awburst_fmt), + .awvalid_s (awvalid_fmt), + .awready_s (awready_fmt), + .awprot_s (awprot_fmt), + .awcache_s (awcache_fmt), + .awlock_s (awlock_fmt), + .awuser_s (awuser_fmt), + .awregion_s (awregion_fmt), + .awid_m (awid_bif), + .awaddr_m (awaddr_bif), + .awlen_m (awlen_bif), + .awsize_m (awsize_bif), + .awburst_m (awburst_bif), + .awvalid_m (awvalid_bif), + .awready_m (awready_bif), + .awprot_m (awprot_bif), + .awlock_m (awlock_bif), + .awcache_m (awcache_bif), + .awuser_m (awuser_bif), + .awregion_m (awregion_bif) + ); + assign awvalid_vect_bif = awvalid_vect_fmt; + assign awqv_bif = awqv_fmt; +upsize_wr_cntrl #( + .ARID_WIDTH(ARID_WIDTH), + .AWID_WIDTH(AWID_WIDTH), + .ADDR_WIDTH(ADDR_WIDTH), + .US_DATA_WIDTH(US_DATA_WIDTH), + .DS_DATA_WIDTH(DS_DATA_WIDTH), + .USER_WIDTH(USER_WIDTH) + ) u_upsize_axi_write_control + ( + .aresetn (aresetn), + .aclk (aclk), + .awfifo_valid (awdata_valid), + .awfifo_ready (awdata_ready), + .awfifo_data (awdata_data), + .wvalid_s (wvalid_axi_r), + .wready_s (wready_axi_r), + .wlast (wlast_axi_r), + .wuser (wuser_axi_r), + .wid (wid_axi_r), + .merge (merge), + .merge_clear (merge_clear), + .data_select (data_select), + .strb_skid_valid (strb_skid_valid), + .wdata_merged (wdata_merged), + .wstrb_merged (wstrb_merged), + .wvalid_m (wvalid_bif), + .wready_m (wready_bif), + .wlast_m (wlast_bif), + .wuser_m (wuser_bif), + .wid_m (wid_bif), + .wdata_m (wdata_bif), + .wstrb_m (wstrb_bif) + ); + upsize_wr_merge_buffer #( + .US_DATA_WIDTH(US_DATA_WIDTH), + .DS_DATA_WIDTH(DS_DATA_WIDTH) + ) u_upsize_axi_write_merge_buffer + ( + .aresetn (aresetn), + .aclk (aclk), + .wdata_out (wdata_merged), + .wstrb_out (wstrb_merged), + .wdata_in (wdata_axi_r), + .wstrb_in (wstrb_axi_r), + .data_select (data_select), + .merge_skid_valid (strb_skid_valid), + .merge (merge), + .merge_clear (merge_clear) + ); + upsize_wr_resp_block #( + .AWID_WIDTH(AWID_WIDTH), + .USER_WIDTH(USER_WIDTH), + .WR_ISS(WR_ISS) + ) u_upsize_axi_write_response_block + ( + .aclk (aclk), + .aresetn (aresetn), + .bchannel_ready (bdata_ready), + .bchannel_valid (bdata_valid), + .bchannel_data (bdata_data), + .bready_s (bready_axi_r), + .bvalid_s (bvalid_axi_r), + .bid_s (bid_axi_r), + .buser_s (buser_axi_r), + .bresp_s (bresp_axi_r), + .buser_m (buser_bif), + .bresp_m (bresp_bif), + .bid_m (bid_bif), + .bvalid_m (bvalid_bif), + .bready_m (bready_bif) + ); + assign ar_fmt_src_data = { + arregion_axi_r, + aruser_axi_r, + arid_axi_r, + araddr_axi_r, + arlen_axi_r, + arsize_axi_r, + arburst_axi_r, + arlock_axi_r, + arcache_axi_r, + arqv_axi_r, + arprot_axi_r, + arvalid_vect_axi_r}; + assign arvalid_fmt = arvalid_axi_r; + assign arready_axi_r = arready_fmt; + assign ar_fmt_dst_data = ar_fmt_src_data; + assign { + arregion_fmt, + aruser_fmt, + arid_fmt, + araddr_fmt, + arlen_fmt, + arsize_fmt, + arburst_fmt, + arlock_fmt, + arcache_fmt, + arqv_fmt, + arprot_fmt, + arvalid_vect_fmt} = ar_fmt_dst_data; + upsize_rd_addr_fmt #( + .ARID_WIDTH(ARID_WIDTH), + .AWID_WIDTH(AWID_WIDTH), + .ADDR_WIDTH(ADDR_WIDTH), + .US_DATA_WIDTH(US_DATA_WIDTH), + .DS_DATA_WIDTH(DS_DATA_WIDTH), + .USER_WIDTH(USER_WIDTH), + .DS_AXI3(DS_AXI3) + ) u_axi_read_address_format + ( + .aresetn (aresetn), + .aclk (aclk), + .lock_seq (lock_seq), + .ar_lock_hndshk (ar_lock_hndshk), + .ar_unlock_hndshk (ar_unlock_hndshk), + .ardata_valid (arfifo_valid), + .ardata_ready (arfifo_ready), + .ardata_data (arfifo_data), + .arid_s (arid_fmt), + .araddr_s (araddr_fmt), + .arlen_s (arlen_fmt), + .arsize_s (arsize_fmt), + .arburst_s (arburst_fmt), + .arvalid_s (arvalid_fmt), + .arready_s (arready_fmt), + .arprot_s (arprot_fmt), + .arcache_s (arcache_fmt), + .arlock_s (arlock_fmt), + .aruser_s (aruser_fmt), + .arregion_s (arregion_fmt), + .arid_m (arid_bif), + .araddr_m (araddr_bif), + .arlen_m (arlen_bif), + .arsize_m (arsize_bif), + .arburst_m (arburst_bif), + .arvalid_m (arvalid_bif), + .arready_m (arready_bif), + .arprot_m (arprot_bif), + .arlock_m (arlock_bif), + .aruser_m (aruser_bif), + .arregion_m (arregion_bif), + .arcache_m (arcache_bif) + ); + assign arvalid_vect_bif = arvalid_vect_fmt; + assign arqv_bif = arqv_fmt; + upsize_rd_chan + #( +.ARID_WIDTH (ARID_WIDTH ), +.AWID_WIDTH (AWID_WIDTH ), +.ADDR_WIDTH (ADDR_WIDTH ), +.US_DATA_WIDTH (US_DATA_WIDTH), +.DS_DATA_WIDTH (DS_DATA_WIDTH), +.USER_WIDTH (USER_WIDTH ), +.RD_ISS (RD_ISS ) + ) +u_upsize_axi_read_channel + ( + .aresetn (aresetn), + .aclk (aclk), + .archannel_data (arfifo_data), + .archannel_valid (arfifo_valid), + .archannel_ready (arfifo_ready), + .rvalid_s (rvalid_axi_r), + .rdata_s (rdata_axi_r), + .rlast_s (rlast_axi_r), + .rid_s (rid_axi_r), + .rresp_s (rresp_axi_r), + .ruser_s (ruser_axi_r), + .rready_s (rready_axi_r), + .rvalid_m (rvalid_bif), + .rdata_m (rdata_bif), + .rlast_m (rlast_bif), + .rid_m (rid_bif), + .rresp_m (rresp_bif), + .ruser_m (ruser_bif), + .rready_m (rready_bif) + ); + assign aw_data = { + awregion_bif, + awuser_bif, + awid_bif, + awaddr_bif, + awlen_bif, + awsize_bif, + awburst_bif, + awlock_bif, + awcache_bif, + awqv_bif, + awprot_bif, + awvalid_vect_bif}; + assign aw_valid = awvalid_bif; + assign awready_bif = aw_ready; + assign ar_data = { + arregion_bif, + aruser_bif, + arid_bif, + araddr_bif, + arlen_bif, + arsize_bif, + arburst_bif, + arlock_bif, + arcache_bif, + arqv_bif, + arprot_bif, + arvalid_vect_bif}; + assign ar_valid = arvalid_bif; + assign arready_bif = ar_ready; + assign w_boundary_src_data = { + wid_bif, + wuser_bif, + wdata_bif, + wstrb_bif, + wlast_bif}; + assign w_boundary_src_valid = wvalid_bif; + assign wready_bif = w_boundary_src_ready; + assign w_data = w_boundary_dst_data; + assign w_valid = w_boundary_dst_valid; + assign w_boundary_dst_ready = w_ready; + assign { + ruser_bif, + rid_bif, + rdata_bif, + rresp_bif, + rlast_bif} = r_data; + assign r_ready = rready_bif; + assign rvalid_bif = r_valid; + assign { + buser_bif, + bid_bif, + bresp_bif} = b_data; + assign b_ready = bready_bif; + assign bvalid_bif = b_valid; + assign aw_slave_port_src_data = { + awregion_s, + awuser_s, + awid_s, + awaddr_s, + awlen_s, + awsize_s, + awburst_s, + awlock_s, + awcache_s, + awqv_s, + awprot_s, + awvalid_vect_s}; + assign { + awregion_axi_r, + awuser_axi_r, + awid_axi_r, + awaddr_axi_r, + awlen_axi_r, + awsize_axi_r, + awburst_axi_r, + awlock_axi_r, + awcache_axi_r, + awqv_axi_r, + awprot_axi_r, + awvalid_vect_axi_r} = aw_slave_port_dst_data; + assign awvalid_axi_r = aw_slave_port_dst_valid; + assign aw_slave_port_dst_ready = awready_axi_r; + assign aw_slave_port_src_valid = awvalid_s; + assign awready_s = aw_slave_port_src_ready; + assign ar_slave_port_src_data = { + arregion_s, + aruser_s, + arid_s, + araddr_s, + arlen_s, + arsize_s, + arburst_s, + arlock_s, + arcache_s, + arqv_s, + arprot_s, + arvalid_vect_s}; + assign { + arregion_axi_r, + aruser_axi_r, + arid_axi_r, + araddr_axi_r, + arlen_axi_r, + arsize_axi_r, + arburst_axi_r, + arlock_axi_r, + arcache_axi_r, + arqv_axi_r, + arprot_axi_r, + arvalid_vect_axi_r} = ar_slave_port_dst_data; + assign arvalid_axi_r = ar_slave_port_dst_valid; + assign ar_slave_port_dst_ready = arready_axi_r; + assign ar_slave_port_src_valid = arvalid_s; + assign arready_s = ar_slave_port_src_ready; + assign r_slave_port_src_data = { + ruser_axi_r, + rid_axi_r, + rdata_axi_r, + rresp_axi_r, + rlast_axi_r}; + assign { + ruser_s, + rid_s, + rdata_s, + rresp_s, + rlast_s} = r_slave_port_dst_data; + assign r_slave_port_dst_data = r_slave_port_src_data; + assign rvalid_s = rvalid_axi_r; + assign rready_axi_r = rready_s; + assign w_slave_port_src_data = { + wid_s, + wuser_s, + wdata_s, + wstrb_s, + wlast_s}; + assign { + wid_axi_r, + wuser_axi_r, + wdata_axi_r, + wstrb_axi_r, + wlast_axi_r} = w_slave_port_dst_data; + assign w_slave_port_dst_data = w_slave_port_src_data; + assign wvalid_axi_r = wvalid_s; + assign wready_s = wready_axi_r; + assign b_slave_port_src_data = { + buser_axi_r, + bid_axi_r, + bresp_axi_r}; + assign { + buser_s, + bid_s, + bresp_s} = b_slave_port_dst_data; + assign b_slave_port_dst_data = b_slave_port_src_data; + assign bvalid_s = bvalid_axi_r; + assign bready_axi_r = bready_s; + axi_slice + #( + .HNDSHK_MODE (2'h0), + .PAYLD_WIDTH (W_IDB_WIDTH) + ) + u_w_boundary_chan_slice + ( + .aresetn (aresetn), + .aclk (aclk), + .src_valid (w_boundary_src_valid), + .src_data (w_boundary_src_data), + .dst_ready (w_boundary_dst_ready), + .src_ready (w_boundary_src_ready), + .dst_data (w_boundary_dst_data), + .dst_valid (w_boundary_dst_valid) + ); + axi_slice + #( + .HNDSHK_MODE (2'h0), + .PAYLD_WIDTH (US_AW_WIDTH) + ) + u_aw_slave_port_chan_slice + ( + .aresetn (aresetn), + .aclk (aclk), + .src_valid (aw_slave_port_src_valid), + .src_data (aw_slave_port_src_data), + .dst_ready (aw_slave_port_dst_ready), + .src_ready (aw_slave_port_src_ready), + .dst_data (aw_slave_port_dst_data), + .dst_valid (aw_slave_port_dst_valid) + ); + axi_slice + #( + .HNDSHK_MODE (2'h0), + .PAYLD_WIDTH (US_AR_WIDTH) + ) + u_ar_slave_port_chan_slice + ( + .aresetn (aresetn), + .aclk (aclk), + .src_valid (ar_slave_port_src_valid), + .src_data (ar_slave_port_src_data), + .dst_ready (ar_slave_port_dst_ready), + .src_ready (ar_slave_port_src_ready), + .dst_data (ar_slave_port_dst_data), + .dst_valid (ar_slave_port_dst_valid) + ); +endmodule +`include "Axi_undefs.v"
diff --git a/axi2sramcrs/rtl/upsizer/upsize_wr_addr_fmt.v b/axi2sramcrs/rtl/upsizer/upsize_wr_addr_fmt.v new file mode 100644 index 0000000..8db1554 --- /dev/null +++ b/axi2sramcrs/rtl/upsizer/upsize_wr_addr_fmt.v
@@ -0,0 +1,1049 @@ +//**************************************************************************** +// +// Copyright 2017-2023 Vivante Corporation +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +//**************************************************************************** +// Auto-generated file on 11/03/2023. +// +//**************************************************************************** + +module upsize_wr_addr_fmt + ( + lock_seq, bdata_data, bdata_valid, awfmt_valid, awfmt_data, + awready_s, awid_m, awaddr_m, awlen_m, awsize_m, awburst_m, + awcache_m, awprot_m, awlock_m, awvalid_m, awuser_m, awregion_m, + aclk, aresetn, ar_lock_hndshk, ar_unlock_hndshk, bdata_ready, + awfmt_ready, awid_s, awaddr_s, awlen_s, awsize_s, awburst_s, + awcache_s, awprot_s, awvalid_s, awlock_s, awuser_s, awregion_s, + awready_m + ); +`include "Axi.v" +parameter ARID_WIDTH=4; +parameter AWID_WIDTH=4; +parameter ADDR_WIDTH=32; +parameter US_DATA_WIDTH=128; +parameter DS_DATA_WIDTH=256; +parameter USER_WIDTH=4; +parameter DS_AXI3=1'h1; +localparam DS_WSTRB_WIDTH=DS_DATA_WIDTH/8; +localparam US_WSTRB_WIDTH=US_DATA_WIDTH/8; +localparam DS_ADDR_AL_WIDTH=$clog2(DS_WSTRB_WIDTH); +localparam US_ADDR_AL_WIDTH=$clog2(US_WSTRB_WIDTH); +localparam AWFMT_WIDTH=AWID_WIDTH+1+4+1+DS_ADDR_AL_WIDTH*2+3+1; +localparam US_AW_WIDTH=4+USER_WIDTH+AWID_WIDTH+ADDR_WIDTH+8+3+2+2+4+4+3+1; +localparam US_AR_WIDTH=4+USER_WIDTH+ARID_WIDTH+ADDR_WIDTH+8+3+2+2+4+4+3+1; +localparam US_R_WIDTH=USER_WIDTH+ARID_WIDTH+US_DATA_WIDTH+2+1; +localparam US_W_WIDTH=USER_WIDTH+AWID_WIDTH+US_DATA_WIDTH+US_WSTRB_WIDTH+1; +localparam US_B_WIDTH=USER_WIDTH+AWID_WIDTH+2; +localparam AW_IDB_WIDTH=US_AW_WIDTH; +localparam W_IDB_WIDTH=USER_WIDTH+US_DATA_WIDTH+US_WSTRB_WIDTH+1; +localparam B_IDB_WIDTH=USER_WIDTH+2+AWID_WIDTH; +localparam BCHAN_WIDTH=AWID_WIDTH+1; +localparam WDATA_CAM_WIDTH_UP =DS_ADDR_AL_WIDTH-US_ADDR_AL_WIDTH; +localparam TOTAL_BYTES_WIDTH = US_ADDR_AL_WIDTH+8; + input aclk; + input aresetn; + input ar_lock_hndshk; + input ar_unlock_hndshk; + output lock_seq; + output [BCHAN_WIDTH-1:0] bdata_data; + output bdata_valid; + input bdata_ready; + input awfmt_ready; + output awfmt_valid; + output [AWFMT_WIDTH-1:0] awfmt_data; + input [AWID_WIDTH-1:0] awid_s; + input [ADDR_WIDTH-1:0] awaddr_s; + input [7:0] awlen_s; + input [2:0] awsize_s; + input [1:0] awburst_s; + input [3:0] awcache_s; + input [2:0] awprot_s; + input awvalid_s; + input [1:0] awlock_s; + output awready_s; + input [USER_WIDTH-1:0] awuser_s; + input [3:0] awregion_s; + output [AWID_WIDTH-1:0] awid_m; + output [ADDR_WIDTH-1:0] awaddr_m; + output [7:0] awlen_m; + output [2:0] awsize_m; + output [1:0] awburst_m; + output [3:0] awcache_m; + output [2:0] awprot_m; + output [1:0] awlock_m; + output awvalid_m; + input awready_m; + output [USER_WIDTH-1:0] awuser_m; + output [3:0] awregion_m; + reg [ADDR_WIDTH-1:0] awaddro; // transaction start address (int) + reg [7:0] awleno; // transaction length (int) + reg [2:0] awsizeo; // transaction transfer size (int) + reg [1:0] awbursto; // transaction burst type (int) + reg [AWID_WIDTH-1:0] awido; + reg [3:0] awcacheo; + reg [2:0] awproto; + reg [1:0] awlocko; + reg [USER_WIDTH-1:0] awusero; + reg [3:0] awregiono; + reg excl_override_reg; + reg busy_reg; + reg [TOTAL_BYTES_WIDTH-1:0] wrap_bytes_remaining_reg; + reg [DS_ADDR_AL_WIDTH-1:0] write_mask; + wire n_response; + reg [TOTAL_BYTES_WIDTH-1:0] total_bytes; + reg [TOTAL_BYTES_WIDTH-1:0] total_bytes_masked; + reg [2:0] wrapsize; + reg [2:0] wrapfitsize; + reg [3:0] wraplen; + reg [DS_ADDR_AL_WIDTH:0] wrapalignmask; + reg wrap_split_reg; + reg [2:0] incrsize; + reg lock_seq; + wire slave_hndshk; + wire master_hndshk; + wire bypass; + wire [ADDR_WIDTH-1:0] awaddr_aligned; + wire [DS_ADDR_AL_WIDTH+8-1:0] total_bytes_ext; + wire [TOTAL_BYTES_WIDTH-1:0] wrap_boundary_mask; + wire wrap_aligned; + wire wrap_is_incr; + wire wrap_split; + wire wrap_fits; + wire [TOTAL_BYTES_WIDTH-1:0] wrap_fits_mask; + wire [DS_ADDR_AL_WIDTH:0] working_addr; + wire wrap_split_reg_nxt; + wire wrap_split_reg_wr_en; + wire wrap_info_write_en; + wire [TOTAL_BYTES_WIDTH-1:0] next_wrap_bytes_remaining_reg; + wire [TOTAL_BYTES_WIDTH-1:0] addr_less_one; + wire [7:0] wraplen_i; + wire [7:0] awlen_1; + wire [7:0] incrlen; + wire [TOTAL_BYTES_WIDTH-1:0] bytes_to_transfer; + wire [TOTAL_BYTES_WIDTH+8-1:0] bytes_to_transfer_large; + wire [TOTAL_BYTES_WIDTH-1:0] bytes_to_transfer_wrap1; + wire [DS_ADDR_AL_WIDTH-1:0] offset_address; + wire [7:0] incrlenmaxsize; + wire [DS_ADDR_AL_WIDTH:0] final_address; + wire overflow; + wire bytes_lt_one_byte; + wire bytes_lt_two_byte; + wire bytes_lt_two_half; + wire bytes_lt_four_half; + wire half_carry; + wire half_carry_double; + wire bytes_lt_four_word; + wire bytes_lt_eight_word; + wire [2:0] word_carry; + wire word_carry_double; + wire bytes_lt_eight_dword; + wire bytes_lt_sixt_dword; + wire [3:0] dword_carry; + wire dword_carry_double; + wire bytes_lt_sixt_qword; + wire bytes_lt_ttwo_qword; + wire [4:0] qword_carry; + wire qword_carry_double; + wire bytes_lt_ttwo_oword; + wire bytes_lt_sfour_oword; + wire [5:0] oword_carry; + wire oword_carry_double; + wire buffers_ok; + wire new_transaction; + wire trans_in_progress; + wire new_trans_avail; + wire trans_complete; + wire next_busy_reg; + wire busy_reg_wr_en; + wire excl_override; + assign slave_hndshk = awvalid_s & awready_s; + assign master_hndshk = awvalid_m & awready_m; +assign awfmt_data = { + awid_s, + wrap_split, + awleno[3:0], + wrap_fits, + write_mask, + awaddr_s[DS_ADDR_AL_WIDTH-1:0], + awsize_s, + bypass || (awburst_s == `AXI_ABURST_FIXED) + }; + assign awfmt_valid = new_transaction; + always @(*) + begin : p_new_addr_incr_en_w + write_mask = {DS_ADDR_AL_WIDTH{1'b0}}; + case (awburst_s) + `AXI_ABURST_FIXED : write_mask = {DS_ADDR_AL_WIDTH{1'b0}}; + `AXI_ABURST_WRAP : write_mask = total_bytes[DS_ADDR_AL_WIDTH-1:0]; + `AXI_ABURST_INCR : write_mask = {DS_ADDR_AL_WIDTH{1'b1}}; + default : write_mask = {DS_ADDR_AL_WIDTH{1'b0}}; + endcase + end + assign bdata_data = {awid_s, n_response}; + assign bdata_valid = new_transaction; + assign n_response = wrap_split; + assign buffers_ok = bdata_ready & awfmt_ready; + assign trans_complete = ~((wrap_split & ~wrap_split_reg) ); + assign trans_in_progress = new_transaction | busy_reg; + assign new_transaction = new_trans_avail & buffers_ok; + assign new_trans_avail = awvalid_s & ~busy_reg; + assign next_busy_reg = (trans_complete & slave_hndshk) ? 1'b0 : + ((new_transaction & ~slave_hndshk) ? 1'b1 : busy_reg); + assign busy_reg_wr_en = busy_reg ^ next_busy_reg; + always @(posedge aclk or negedge aresetn) + begin : busy_reg_p + if (!aresetn) begin + busy_reg <= 1'b0; + end else if (busy_reg_wr_en) begin + busy_reg <= next_busy_reg; + end + end + assign excl_override = (new_transaction) ? n_response | (|awleno[7:4]) : excl_override_reg; + always @(posedge aclk or negedge aresetn) + begin : excl_override_reg_p + if (!aresetn) begin + excl_override_reg <= 1'b0; + end else if (new_transaction) begin + excl_override_reg <= excl_override; + end + end + assign awregion_m = awregiono; + assign awuser_m = awusero; + assign awid_m = awido; + assign awcache_m = awcacheo; + assign awprot_m = awproto; + assign awlen_m = awleno; + assign awsize_m = awsizeo; + assign awaddr_m = awaddro; + assign awburst_m = awbursto; + assign awlock_m = awlocko; + assign awvalid_m = awvalid_s && trans_in_progress; + assign awready_s = master_hndshk && trans_complete; + always @(*) begin + awleno = incrlen; + awsizeo = incrsize; + awbursto = `AXI_ABURST_INCR; + awido = awid_s; + awusero = awuser_s; + awregiono = awregion_s; + awcacheo = awcache_s; + awproto = awprot_s; + awaddro = awaddr_aligned; + awlocko = {(awlock_s[1] | (lock_seq & ~trans_complete)),(awlock_s[0] && (~excl_override))}; + if (!wrap_split_reg) begin + awaddro = awaddr_s; + if (wrap_aligned) begin + awleno = wraplen_i; + awsizeo = wrapsize; + awbursto = `AXI_ABURST_WRAP; + end else if (bypass) begin + awleno = awlen_s; + awsizeo = awsize_s; + awbursto = awburst_s; + end else if (wrap_fits) begin + awaddro = awaddr_aligned; + awleno = awlen_1; + awsizeo = wrapfitsize; + awbursto = `AXI_ABURST_INCR; + end + end + end + assign wraplen_i = {4'b0000,wraplen}; + assign awlen_1 = {4'b0000,`AXI_ALEN_1}; + assign addr_less_one = awaddr_s[TOTAL_BYTES_WIDTH-1:0] - {{TOTAL_BYTES_WIDTH{1'b0}},1'b1}; + assign next_wrap_bytes_remaining_reg = (addr_less_one & total_bytes); + assign wrap_info_write_en = wrap_split & master_hndshk; + always @(posedge aclk or negedge aresetn) + begin : wrap_bytes_remaining_reg_p + if (!aresetn) begin + wrap_bytes_remaining_reg <= {TOTAL_BYTES_WIDTH{1'b0}}; + end else if (wrap_info_write_en) begin + wrap_bytes_remaining_reg <= next_wrap_bytes_remaining_reg; + end + end + assign awaddr_aligned = {awaddr_s[ADDR_WIDTH-1:TOTAL_BYTES_WIDTH],((awaddr_s[TOTAL_BYTES_WIDTH-1:0]) & (~total_bytes))}; + assign wrap_split_reg_nxt = wrap_split & ~(wrap_split_reg); + assign wrap_split_reg_wr_en = master_hndshk; + always @(posedge aclk or negedge aresetn) + begin : wrap_split_p + if (!aresetn) + wrap_split_reg <= 1'b0; + else if (wrap_split_reg_wr_en) + wrap_split_reg <= wrap_split_reg_nxt; + end + assign next_lock_seq = (ar_lock_hndshk | (slave_hndshk & awlock_s[1])) ? + 1'b1 : ((ar_unlock_hndshk | (master_hndshk & ~awlock_m[1])) ? + 1'b0 : lock_seq); + always @(posedge aclk or negedge aresetn) + begin : locked_sequence_reg + if (!aresetn) + lock_seq <= 1'b0; + else if (master_hndshk || slave_hndshk || ar_lock_hndshk || ar_unlock_hndshk) + lock_seq <= next_lock_seq; + end + assign bypass = (awburst_s == `AXI_ABURST_FIXED ) || ~awcache_s[1] || (awlen_s == `AXI_ALEN_1); +generate + if( US_DATA_WIDTH == 32 ) + begin + always @(*) + begin : total_bytes_p32 + case (awsize_s) + `AXI_ASIZE_8 : + total_bytes = { {(TOTAL_BYTES_WIDTH-8){1'b0}}, awlen_s}; + `AXI_ASIZE_16 : + total_bytes = { {(TOTAL_BYTES_WIDTH-8-1){1'b0}}, awlen_s, 1'b1}; + `AXI_ASIZE_32 : + total_bytes = { awlen_s, 2'b11}; + default : + total_bytes = { {(TOTAL_BYTES_WIDTH-8){1'b0}}, awlen_s}; + endcase + end + end + else if( US_DATA_WIDTH == 64 ) + begin + always @(*) + begin : total_bytes_p64 + case (awsize_s) + `AXI_ASIZE_8 : + total_bytes = { {(TOTAL_BYTES_WIDTH-8){1'b0}}, awlen_s}; + `AXI_ASIZE_16 : + total_bytes = { {(TOTAL_BYTES_WIDTH-8-1){1'b0}}, awlen_s, 1'b1}; + `AXI_ASIZE_32 : + total_bytes = { {(TOTAL_BYTES_WIDTH-8-2){1'b0}}, awlen_s, 2'b11}; + `AXI_ASIZE_64 : + total_bytes = { awlen_s, 3'b111}; + default : + total_bytes = { {(TOTAL_BYTES_WIDTH-8){1'b0}}, awlen_s}; + endcase + end + end + else if( US_DATA_WIDTH == 128 ) + begin + always @(*) + begin : total_bytes_p128 + case (awsize_s) + `AXI_ASIZE_8 : + total_bytes = { {(TOTAL_BYTES_WIDTH-8){1'b0}}, awlen_s}; + `AXI_ASIZE_16 : + total_bytes = { {(TOTAL_BYTES_WIDTH-8-1){1'b0}}, awlen_s, 1'b1}; + `AXI_ASIZE_32 : + total_bytes = { {(TOTAL_BYTES_WIDTH-8-2){1'b0}}, awlen_s, 2'b11}; + `AXI_ASIZE_64 : + total_bytes = { {(TOTAL_BYTES_WIDTH-8-3){1'b0}}, awlen_s, 3'b111}; + `AXI_ASIZE_128 : + total_bytes = { awlen_s, 4'b1111}; + default : + total_bytes = { {(TOTAL_BYTES_WIDTH-8){1'b0}}, awlen_s}; + endcase + end + end + else if( US_DATA_WIDTH == 256 ) + begin + always @(*) + begin : total_bytes_p256 + case (awsize_s) + `AXI_ASIZE_8 : + total_bytes = { {(TOTAL_BYTES_WIDTH-8){1'b0}}, awlen_s}; + `AXI_ASIZE_16 : + total_bytes = { {(TOTAL_BYTES_WIDTH-8-1){1'b0}}, awlen_s, 1'b1}; + `AXI_ASIZE_32 : + total_bytes = { {(TOTAL_BYTES_WIDTH-8-2){1'b0}}, awlen_s, 2'b11}; + `AXI_ASIZE_64 : + total_bytes = { {(TOTAL_BYTES_WIDTH-8-3){1'b0}}, awlen_s, 3'b111}; + `AXI_ASIZE_128 : + total_bytes = { {(TOTAL_BYTES_WIDTH-8-4){1'b0}}, awlen_s, 4'b1111}; + `AXI_ASIZE_256 : + total_bytes = { awlen_s, 5'b11111}; + default : + total_bytes = { {(TOTAL_BYTES_WIDTH-8){1'b0}}, awlen_s}; + endcase + end + end + else if( US_DATA_WIDTH == 512 ) + begin + always @(*) + begin : total_bytes_p512 + case (awsize_s) + `AXI_ASIZE_8 : + total_bytes = { {(TOTAL_BYTES_WIDTH-8){1'b0}}, awlen_s}; + `AXI_ASIZE_16 : + total_bytes = { {(TOTAL_BYTES_WIDTH-8-1){1'b0}}, awlen_s, 1'b1}; + `AXI_ASIZE_32 : + total_bytes = { {(TOTAL_BYTES_WIDTH-8-2){1'b0}}, awlen_s, 2'b11}; + `AXI_ASIZE_64 : + total_bytes = { {(TOTAL_BYTES_WIDTH-8-3){1'b0}}, awlen_s, 3'b111}; + `AXI_ASIZE_128 : + total_bytes = { {(TOTAL_BYTES_WIDTH-8-4){1'b0}}, awlen_s, 4'b1111}; + `AXI_ASIZE_256 : + total_bytes = { {(TOTAL_BYTES_WIDTH-8-5){1'b0}}, awlen_s, 5'b11111}; + `AXI_ASIZE_512 : + total_bytes = { awlen_s, 6'b111111}; + default : + total_bytes = { {(TOTAL_BYTES_WIDTH-8){1'b0}}, awlen_s}; + endcase + end + end + else + begin + always @(*) + begin : total_bytes_p_others + case (awsize_s) + `AXI_ASIZE_8 : + total_bytes = { {(TOTAL_BYTES_WIDTH-8){1'b0}}, awlen_s}; + `AXI_ASIZE_16 : + total_bytes = { {(TOTAL_BYTES_WIDTH-8-1){1'b0}}, awlen_s, 1'b1}; + `AXI_ASIZE_32 : + total_bytes = { {(TOTAL_BYTES_WIDTH-8-2){1'b0}}, awlen_s, 2'b11}; + `AXI_ASIZE_64 : + total_bytes = { {(TOTAL_BYTES_WIDTH-8-3){1'b0}}, awlen_s, 3'b111}; + `AXI_ASIZE_128 : + total_bytes = { {(TOTAL_BYTES_WIDTH-8-4){1'b0}}, awlen_s, 4'b1111}; + `AXI_ASIZE_256 : + total_bytes = { {(TOTAL_BYTES_WIDTH-8-5){1'b0}}, awlen_s, 5'b11111}; + `AXI_ASIZE_512 : + total_bytes = { awlen_s, 6'b111111}; + default : + total_bytes = { {(TOTAL_BYTES_WIDTH-8){1'b0}}, awlen_s}; + endcase + end + end +endgenerate + + assign total_bytes_ext = { {WDATA_CAM_WIDTH_UP{1'b0}},total_bytes }; + + +generate + + +if(DS_DATA_WIDTH==512) begin:wrmsk512 + always @(*) + begin : wrap_size_len + + if (total_bytes_ext[6]&&(DS_DATA_WIDTH>=512)) begin + wrapfitsize = `AXI_ASIZE_1024; + wrapsize = `AXI_ASIZE_512; + wraplen = total_bytes_ext[9:6]; + wrapalignmask = {1'b0, 6'b111111}; + end else if (total_bytes_ext[5]&&(DS_DATA_WIDTH>=256)) begin + wrapfitsize = `AXI_ASIZE_512; + wrapsize = `AXI_ASIZE_256; + wraplen = total_bytes_ext[8:5]; + wrapalignmask = {2'b0, 5'b11111}; + end else if (total_bytes_ext[4]&&(DS_DATA_WIDTH>=128)) begin + wrapfitsize = `AXI_ASIZE_256; + wrapsize = `AXI_ASIZE_128; + wraplen = total_bytes_ext[7:4]; + wrapalignmask = {3'b0, 4'b1111}; + end else if (total_bytes_ext[3]&&(DS_DATA_WIDTH>=64)) begin + wrapfitsize = `AXI_ASIZE_128; + wrapsize = `AXI_ASIZE_64; + wraplen = total_bytes_ext[6:3]; + wrapalignmask = {4'b0, 3'b111}; + end else if (total_bytes_ext[2]&&(DS_DATA_WIDTH>=32)) begin + wrapfitsize = `AXI_ASIZE_64; + wrapsize = `AXI_ASIZE_32; + wraplen = total_bytes_ext[5:2]; + wrapalignmask = {5'b0, 2'b11}; + end else if (total_bytes_ext[1]&&(DS_DATA_WIDTH>=16)) begin + wrapfitsize = `AXI_ASIZE_32; + wrapsize = `AXI_ASIZE_16; + wraplen = total_bytes_ext[4:1]; + wrapalignmask = {6'b0, 1'b1}; + end else if (total_bytes_ext[0]&&(DS_DATA_WIDTH>=8))begin + wrapfitsize = `AXI_ASIZE_16; + wrapsize = `AXI_ASIZE_8; + wraplen = total_bytes_ext[3:0]; + wrapalignmask = 7'b0; + end else begin + wrapfitsize = 3'b0; + wrapsize = 3'b0; + wraplen = 4'b0; + wrapalignmask = 7'b0; + end + end + end + + +if(DS_DATA_WIDTH==256) begin:wrmsk256 + always @(*) + begin : wrap_size_len + + if (total_bytes_ext[5]&&(DS_DATA_WIDTH>=256)) begin + wrapfitsize = `AXI_ASIZE_512; + wrapsize = `AXI_ASIZE_256; + wraplen = total_bytes_ext[8:5]; + wrapalignmask = {2'b0, 5'b11111}; + end else if (total_bytes_ext[4]&&(DS_DATA_WIDTH>=128)) begin + wrapfitsize = `AXI_ASIZE_256; + wrapsize = `AXI_ASIZE_128; + wraplen = total_bytes_ext[7:4]; + wrapalignmask = {3'b0, 4'b1111}; + end else if (total_bytes_ext[3]&&(DS_DATA_WIDTH>=64)) begin + wrapfitsize = `AXI_ASIZE_128; + wrapsize = `AXI_ASIZE_64; + wraplen = total_bytes_ext[6:3]; + wrapalignmask = {4'b0, 3'b111}; + end else if (total_bytes_ext[2]&&(DS_DATA_WIDTH>=32)) begin + wrapfitsize = `AXI_ASIZE_64; + wrapsize = `AXI_ASIZE_32; + wraplen = total_bytes_ext[5:2]; + wrapalignmask = {5'b0, 2'b11}; + end else if (total_bytes_ext[1]&&(DS_DATA_WIDTH>=16)) begin + wrapfitsize = `AXI_ASIZE_32; + wrapsize = `AXI_ASIZE_16; + wraplen = total_bytes_ext[4:1]; + wrapalignmask = {6'b0, 1'b1}; + end else if (total_bytes_ext[0]&&(DS_DATA_WIDTH>=8))begin + wrapfitsize = `AXI_ASIZE_16; + wrapsize = `AXI_ASIZE_8; + wraplen = total_bytes_ext[3:0]; + wrapalignmask = 7'b0; + end else begin + wrapfitsize = 3'b0;//x; + wrapsize = 3'b0;//x; + wraplen = 4'b0;//x; + wrapalignmask = 7'b0;//x; + end + end + end + + +if(DS_DATA_WIDTH==128) begin:wrmsk128 + always @(*) + begin : wrap_size_len + + if (total_bytes_ext[4]&&(DS_DATA_WIDTH>=128)) begin + wrapfitsize = `AXI_ASIZE_256; + wrapsize = `AXI_ASIZE_128; + wraplen = total_bytes_ext[7:4]; + wrapalignmask = {3'b0, 4'b1111}; + end else if (total_bytes_ext[3]&&(DS_DATA_WIDTH>=64)) begin + wrapfitsize = `AXI_ASIZE_128; + wrapsize = `AXI_ASIZE_64; + wraplen = total_bytes_ext[6:3]; + wrapalignmask = {4'b0, 3'b111}; + end else if (total_bytes_ext[2]&&(DS_DATA_WIDTH>=32)) begin + wrapfitsize = `AXI_ASIZE_64; + wrapsize = `AXI_ASIZE_32; + wraplen = total_bytes_ext[5:2]; + wrapalignmask = {5'b0, 2'b11}; + end else if (total_bytes_ext[1]&&(DS_DATA_WIDTH>=16)) begin + wrapfitsize = `AXI_ASIZE_32; + wrapsize = `AXI_ASIZE_16; + wraplen = total_bytes_ext[4:1]; + wrapalignmask = {6'b0, 1'b1}; + end else if (total_bytes_ext[0]&&(DS_DATA_WIDTH>=8))begin + wrapfitsize = `AXI_ASIZE_16; + wrapsize = `AXI_ASIZE_8; + wraplen = total_bytes_ext[3:0]; + wrapalignmask = 7'b0; + end else begin + wrapfitsize = 3'b0; + wrapsize = 3'b0; + wraplen = 4'b0; + wrapalignmask = 7'b0; + end + end + end + + + +if(DS_DATA_WIDTH==64) begin:wrmsk64 + always @(*) + begin : wrap_size_len + + if (total_bytes_ext[3]&&(DS_DATA_WIDTH>=64)) begin + wrapfitsize = `AXI_ASIZE_128; + wrapsize = `AXI_ASIZE_64; + wraplen = total_bytes_ext[6:3]; + wrapalignmask = {4'b0, 3'b111}; + end else if (total_bytes_ext[2]&&(DS_DATA_WIDTH>=32)) begin + wrapfitsize = `AXI_ASIZE_64; + wrapsize = `AXI_ASIZE_32; + wraplen = total_bytes_ext[5:2]; + wrapalignmask = {5'b0, 2'b11}; + end else if (total_bytes_ext[1]&&(DS_DATA_WIDTH>=16)) begin + wrapfitsize = `AXI_ASIZE_32; + wrapsize = `AXI_ASIZE_16; + wraplen = total_bytes_ext[4:1]; + wrapalignmask = {6'b0, 1'b1}; + end else if (total_bytes_ext[0]&&(DS_DATA_WIDTH>=8))begin + wrapfitsize = `AXI_ASIZE_16; + wrapsize = `AXI_ASIZE_8; + wraplen = total_bytes_ext[3:0]; + wrapalignmask = 7'b0; + end else begin + wrapfitsize = 3'b0; + wrapsize = 3'b0; + wraplen = 4'b0; + wrapalignmask = 7'b0; + end + end + end + + + +if(DS_DATA_WIDTH==32) begin:wrmsk32 + always @(*) + begin : wrap_size_len + if (total_bytes_ext[2]&&(DS_DATA_WIDTH>=32)) begin + wrapfitsize = `AXI_ASIZE_64; + wrapsize = `AXI_ASIZE_32; + wraplen = total_bytes_ext[5:2]; + wrapalignmask = {5'b0, 2'b11}; + end else if (total_bytes_ext[1]&&(DS_DATA_WIDTH>=16)) begin + wrapfitsize = `AXI_ASIZE_32; + wrapsize = `AXI_ASIZE_16; + wraplen = total_bytes_ext[4:1]; + wrapalignmask = {6'b0, 1'b1}; + end else if (total_bytes_ext[0]&&(DS_DATA_WIDTH>=8))begin + wrapfitsize = `AXI_ASIZE_16; + wrapsize = `AXI_ASIZE_8; + wraplen = total_bytes_ext[3:0]; + wrapalignmask = 7'b0; + end else begin + wrapfitsize = 3'b0; + wrapsize = 3'b0; + wraplen = 4'b0; + wrapalignmask = 7'b0; + end + end + end + +endgenerate + + + +/* + + always @(*) + begin : wrap_size_len + if (total_bytes_ext[6]&&(DS_DATA_WIDTH>=512)) begin + wrapfitsize = `AXI_ASIZE_1024; + wrapsize = `AXI_ASIZE_512; + wraplen = total_bytes_ext[9:6]; + wrapalignmask = {1'b0, 6'b111111}; + end else + if (total_bytes_ext[5]&&(DS_DATA_WIDTH>=256)) begin + wrapfitsize = `AXI_ASIZE_512; + wrapsize = `AXI_ASIZE_256; + wraplen = total_bytes_ext[8:5]; + wrapalignmask = {2'b0, 5'b11111}; + end else if (total_bytes_ext[4]&&(DS_DATA_WIDTH>=128)) begin + wrapfitsize = `AXI_ASIZE_256; + wrapsize = `AXI_ASIZE_128; + wraplen = total_bytes_ext[7:4]; + wrapalignmask = {3'b0, 4'b1111}; + end else if (total_bytes_ext[3]&&(DS_DATA_WIDTH>=64)) begin + wrapfitsize = `AXI_ASIZE_128; + wrapsize = `AXI_ASIZE_64; + wraplen = total_bytes_ext[6:3]; + wrapalignmask = {4'b0, 3'b111}; + end else if (total_bytes_ext[2]&&(DS_DATA_WIDTH>=32)) begin + wrapfitsize = `AXI_ASIZE_64; + wrapsize = `AXI_ASIZE_32; + wraplen = total_bytes_ext[5:2]; + wrapalignmask = {5'b0, 2'b11}; + end else if (total_bytes_ext[1]&&(DS_DATA_WIDTH>=16)) begin + wrapfitsize = `AXI_ASIZE_32; + wrapsize = `AXI_ASIZE_16; + wraplen = total_bytes_ext[4:1]; + wrapalignmask = {6'b0, 1'b1}; + end else if (total_bytes_ext[0]&&(DS_DATA_WIDTH>=8))begin + wrapfitsize = `AXI_ASIZE_16; + wrapsize = `AXI_ASIZE_8; + wraplen = total_bytes_ext[3:0]; + wrapalignmask = 7'b0; + end else begin + wrapfitsize = 3'b0; + wrapsize = 3'b0; + wraplen = 4'b0; + wrapalignmask = 7'b0; + end + end + +*/ + + assign working_addr = awaddr_s[DS_ADDR_AL_WIDTH:0] & wrapalignmask[DS_ADDR_AL_WIDTH:0]; + assign wrap_fits_mask = {{(TOTAL_BYTES_WIDTH-DS_ADDR_AL_WIDTH){1'b1}}, {DS_ADDR_AL_WIDTH{1'b0}}}; + assign wrap_fits = ~|(total_bytes & wrap_fits_mask) & (awburst_s == `AXI_ABURST_WRAP); + assign wrap_is_incr = ~|(awaddr_s[TOTAL_BYTES_WIDTH-1:0] & total_bytes); + assign wrap_aligned = ~|working_addr & (awburst_s == `AXI_ABURST_WRAP) & ~bypass & ~wrap_is_incr & ~wrap_fits ; + assign wrap_split = ((|working_addr)) & (awburst_s == `AXI_ABURST_WRAP) & ~bypass & ~wrap_fits; + assign wrap_boundary_mask = total_bytes; + assign bytes_to_transfer_wrap1 = ~(awaddr_s[TOTAL_BYTES_WIDTH-1:0]) & wrap_boundary_mask; + assign bytes_to_transfer = (wrap_split_reg) ? wrap_bytes_remaining_reg + : ((awburst_s == `AXI_ABURST_WRAP) ? bytes_to_transfer_wrap1 + : total_bytes_masked); +generate + if(US_DATA_WIDTH == 32) + begin + always @(*) + begin : total_bytes_masked_p32 + case (awsize_s) + `AXI_ASIZE_8 : + total_bytes_masked = { {(TOTAL_BYTES_WIDTH-8){1'b0}}, awlen_s}; + `AXI_ASIZE_16 : //total_bytes_masked = {5'h0, awlen_s, ~awaddr_s[0]}; + total_bytes_masked = { {(TOTAL_BYTES_WIDTH-8-1){1'b0}}, awlen_s, ~awaddr_s[0]}; + `AXI_ASIZE_32 : //total_bytes_masked = {4'h0, awlen_s, ~awaddr_s[1:0]}; + total_bytes_masked = { awlen_s, ~awaddr_s[1:0]}; + default : + total_bytes_masked = {TOTAL_BYTES_WIDTH{1'b0}}; + endcase + end + end + else if(US_DATA_WIDTH == 64) + begin + always @(*) + begin : total_bytes_masked_p64 + case (awsize_s) + `AXI_ASIZE_8 : + total_bytes_masked = { {(TOTAL_BYTES_WIDTH-8){1'b0}}, awlen_s}; + `AXI_ASIZE_16 : //total_bytes_masked = {5'h0, awlen_s, ~awaddr_s[0]}; + total_bytes_masked = { {(TOTAL_BYTES_WIDTH-8-1){1'b0}} , awlen_s, ~awaddr_s[0]}; + `AXI_ASIZE_32 : //total_bytes_masked = {4'h0, awlen_s, ~awaddr_s[1:0]}; + total_bytes_masked = { {(TOTAL_BYTES_WIDTH-8-2){1'b0}} , awlen_s, ~awaddr_s[1:0]}; + `AXI_ASIZE_64 : //total_bytes_masked = {3'h0, awlen_s, ~awaddr_s[2:0]}; + total_bytes_masked = { awlen_s, ~awaddr_s[2:0]}; + default : + total_bytes_masked = {TOTAL_BYTES_WIDTH{1'b0}}; + endcase + end + end + else if(US_DATA_WIDTH == 128) + begin + always @(*) + begin : total_bytes_masked_p128 + case (awsize_s) + `AXI_ASIZE_8 : + total_bytes_masked = { {(TOTAL_BYTES_WIDTH-8){1'b0}}, awlen_s}; + `AXI_ASIZE_16 : //total_bytes_masked = {5'h0, awlen_s, ~awaddr_s[0]}; + total_bytes_masked = { {(TOTAL_BYTES_WIDTH-8-1){1'b0}} , awlen_s, ~awaddr_s[0]}; + `AXI_ASIZE_32 : //total_bytes_masked = {4'h0, awlen_s, ~awaddr_s[1:0]}; + total_bytes_masked = { {(TOTAL_BYTES_WIDTH-8-2){1'b0}} , awlen_s, ~awaddr_s[1:0]}; + `AXI_ASIZE_64 : //total_bytes_masked = {3'h0, awlen_s, ~awaddr_s[2:0]}; + total_bytes_masked = { {(TOTAL_BYTES_WIDTH-8-3){1'b0}} , awlen_s, ~awaddr_s[2:0]}; + `AXI_ASIZE_128 : //total_bytes_masked = {2'h0, awlen_s, ~awaddr_s[3:0]}; + total_bytes_masked = { awlen_s, ~awaddr_s[3:0]}; + default : + total_bytes_masked = {TOTAL_BYTES_WIDTH{1'b0}}; + endcase + end + end + else if(US_DATA_WIDTH == 256) + begin + always @(*) + begin : total_bytes_masked_p256 + case (awsize_s) + `AXI_ASIZE_8 : + total_bytes_masked = { {(TOTAL_BYTES_WIDTH-8){1'b0}}, awlen_s}; + `AXI_ASIZE_16 : //total_bytes_masked = {5'h0, awlen_s, ~awaddr_s[0]}; + total_bytes_masked = { {(TOTAL_BYTES_WIDTH-8-1){1'b0}}, awlen_s, ~awaddr_s[0]}; + `AXI_ASIZE_32 : //total_bytes_masked = {4'h0, awlen_s, ~awaddr_s[1:0]}; + total_bytes_masked = { {(TOTAL_BYTES_WIDTH-8-2){1'b0}}, awlen_s, ~awaddr_s[1:0]}; + `AXI_ASIZE_64 : //total_bytes_masked = {3'h0, awlen_s, ~awaddr_s[2:0]}; + total_bytes_masked = { {(TOTAL_BYTES_WIDTH-8-3){1'b0}}, awlen_s, ~awaddr_s[2:0]}; + `AXI_ASIZE_128 : //total_bytes_masked = {2'h0, awlen_s, ~awaddr_s[3:0]}; + total_bytes_masked = { {(TOTAL_BYTES_WIDTH-8-4){1'b0}}, awlen_s, ~awaddr_s[3:0]}; + `AXI_ASIZE_256 : //total_bytes_masked = {1'h0, awlen_s, ~awaddr_s[4:0]}; + total_bytes_masked = { awlen_s, ~awaddr_s[4:0]}; + default : + total_bytes_masked = {TOTAL_BYTES_WIDTH{1'b0}}; + endcase + end + end + else if(US_DATA_WIDTH == 512) + begin + always @(*) + begin : total_bytes_masked_p512 + case (awsize_s) + `AXI_ASIZE_8 : + total_bytes_masked = { {(TOTAL_BYTES_WIDTH-8){1'b0}}, awlen_s}; + `AXI_ASIZE_16 : //total_bytes_masked = {5'h0, awlen_s, ~awaddr_s[0]}; + total_bytes_masked = { {(TOTAL_BYTES_WIDTH-8-1){1'b0}}, awlen_s, ~awaddr_s[0]}; + `AXI_ASIZE_32 : //total_bytes_masked = {4'h0, awlen_s, ~awaddr_s[1:0]}; + total_bytes_masked = { {(TOTAL_BYTES_WIDTH-8-2){1'b0}}, awlen_s, ~awaddr_s[1:0]}; + `AXI_ASIZE_64 : //total_bytes_masked = {3'h0, awlen_s, ~awaddr_s[2:0]}; + total_bytes_masked = { {(TOTAL_BYTES_WIDTH-8-3){1'b0}}, awlen_s, ~awaddr_s[2:0]}; + `AXI_ASIZE_128 : //total_bytes_masked = {2'h0, awlen_s, ~awaddr_s[3:0]}; + total_bytes_masked = { {(TOTAL_BYTES_WIDTH-8-4){1'b0}}, awlen_s, ~awaddr_s[3:0]}; + `AXI_ASIZE_256 : //total_bytes_masked = {1'h0, awlen_s, ~awaddr_s[4:0]}; + total_bytes_masked = { {(TOTAL_BYTES_WIDTH-8-5){1'b0}}, awlen_s, ~awaddr_s[4:0]}; + `AXI_ASIZE_512 : total_bytes_masked = { awlen_s, ~awaddr_s[5:0]}; + default : + total_bytes_masked = {TOTAL_BYTES_WIDTH{1'b0}}; + endcase + end + end + else + begin + always @(*) + begin : total_bytes_masked_pothers + case (awsize_s) + `AXI_ASIZE_8 : + total_bytes_masked = { {(TOTAL_BYTES_WIDTH-8){1'b0}}, awlen_s}; + `AXI_ASIZE_16 : //total_bytes_masked = {5'h0, awlen_s, ~awaddr_s[0]}; + total_bytes_masked = { {(TOTAL_BYTES_WIDTH-8-1){1'b0}}, awlen_s, ~awaddr_s[0]}; + `AXI_ASIZE_32 : //total_bytes_masked = {4'h0, awlen_s, ~awaddr_s[1:0]}; + total_bytes_masked = { {(TOTAL_BYTES_WIDTH-8-2){1'b0}}, awlen_s, ~awaddr_s[1:0]}; + `AXI_ASIZE_64 : //total_bytes_masked = {3'h0, awlen_s, ~awaddr_s[2:0]}; + total_bytes_masked = { {(TOTAL_BYTES_WIDTH-8-3){1'b0}}, awlen_s, ~awaddr_s[2:0]}; + `AXI_ASIZE_128 : //total_bytes_masked = {2'h0, awlen_s, ~awaddr_s[3:0]}; + total_bytes_masked = { {(TOTAL_BYTES_WIDTH-8-4){1'b0}}, awlen_s, ~awaddr_s[3:0]}; + `AXI_ASIZE_256 : //total_bytes_masked = {1'h0, awlen_s, ~awaddr_s[4:0]}; + total_bytes_masked = { {(TOTAL_BYTES_WIDTH-8-5){1'b0}}, awlen_s, ~awaddr_s[4:0]}; + `AXI_ASIZE_512 : total_bytes_masked = { awlen_s, ~awaddr_s[5:0]}; + default : + total_bytes_masked = {TOTAL_BYTES_WIDTH{1'b0}}; + endcase + end + end +endgenerate + + assign offset_address = (wrap_split_reg) ? awaddr_aligned[DS_ADDR_AL_WIDTH-1:0] : + awaddr_s[DS_ADDR_AL_WIDTH-1:0]; + assign half_carry = bytes_to_transfer[0] & offset_address[0]; + assign half_carry_double = half_carry & bytes_to_transfer[1]; + assign word_carry = {1'b0, bytes_to_transfer[1:0]} + {1'b0, offset_address[1:0]}; + assign word_carry_double = word_carry[2] & bytes_to_transfer[2]; + generate + if(DS_DATA_WIDTH>=64) begin: dword_carry_64 + assign dword_carry = {1'b0, bytes_to_transfer[2:0]} + {1'b0, offset_address[2:0]}; + assign dword_carry_double = dword_carry[3] & bytes_to_transfer[3]; + end + else begin: dword_carry_useless + assign dword_carry=4'h0; + assign dword_carry_double=1'h0; + end +endgenerate +generate + if(DS_DATA_WIDTH>=128) begin: qword_carry_128 + assign qword_carry = {1'b0, bytes_to_transfer[3:0]} + {1'b0, offset_address[3:0]}; + assign qword_carry_double = qword_carry[4] & bytes_to_transfer[4]; + end + else begin: qword_carry_useless + assign qword_carry=5'h0; + assign qword_carry_double=1'h0; + end +endgenerate +generate + if(DS_DATA_WIDTH>=256) begin: oword_carry_256 + assign oword_carry = {1'b0, bytes_to_transfer[4:0]} + {1'b0, offset_address[4:0]}; + assign oword_carry_double = oword_carry[5] & bytes_to_transfer[5]; + end + else begin: oword_carry_useless + assign oword_carry=6'h0; + assign oword_carry_double=1'h0; + end +endgenerate + +generate + if(DS_DATA_WIDTH == 32) + begin:bytes_lt_32 + assign bytes_lt_one_byte = ~|bytes_to_transfer; + assign bytes_lt_two_byte = ~|bytes_to_transfer[TOTAL_BYTES_WIDTH-1:1]; + assign bytes_lt_two_half = ~|bytes_to_transfer[TOTAL_BYTES_WIDTH-1:1] & ~half_carry; + assign bytes_lt_four_half = ~|bytes_to_transfer[TOTAL_BYTES_WIDTH-1:2] & ~half_carry_double; + assign bytes_lt_four_word = ~|bytes_to_transfer[TOTAL_BYTES_WIDTH-1:2] & ~word_carry[2]; + end + else if(DS_DATA_WIDTH == 64) + begin:bytes_lt_64 + assign bytes_lt_one_byte = ~|bytes_to_transfer; + assign bytes_lt_two_byte = ~|bytes_to_transfer[TOTAL_BYTES_WIDTH-1:1]; + assign bytes_lt_two_half = ~|bytes_to_transfer[TOTAL_BYTES_WIDTH-1:1] & ~half_carry; + assign bytes_lt_four_half = ~|bytes_to_transfer[TOTAL_BYTES_WIDTH-1:2] & ~half_carry_double; + assign bytes_lt_four_word = ~|bytes_to_transfer[TOTAL_BYTES_WIDTH-1:2] & ~word_carry[2]; + assign bytes_lt_eight_word = ~|bytes_to_transfer[TOTAL_BYTES_WIDTH-1:3] & ~word_carry_double; + assign bytes_lt_eight_dword = ~|bytes_to_transfer[TOTAL_BYTES_WIDTH-1:3] & ~dword_carry[3]; + assign bytes_lt_sixt_dword = ~|bytes_to_transfer[TOTAL_BYTES_WIDTH-1:4] & ~dword_carry_double; + end + else if(DS_DATA_WIDTH == 128) + begin:bytes_lt_128 + assign bytes_lt_one_byte = ~|bytes_to_transfer; + assign bytes_lt_two_byte = ~|bytes_to_transfer[TOTAL_BYTES_WIDTH-1:1]; + assign bytes_lt_two_half = ~|bytes_to_transfer[TOTAL_BYTES_WIDTH-1:1] & ~half_carry; + assign bytes_lt_four_half = ~|bytes_to_transfer[TOTAL_BYTES_WIDTH-1:2] & ~half_carry_double; + assign bytes_lt_four_word = ~|bytes_to_transfer[TOTAL_BYTES_WIDTH-1:2] & ~word_carry[2]; + assign bytes_lt_eight_word = ~|bytes_to_transfer[TOTAL_BYTES_WIDTH-1:3] & ~word_carry_double; + assign bytes_lt_eight_dword = ~|bytes_to_transfer[TOTAL_BYTES_WIDTH-1:3] & ~dword_carry[3]; + assign bytes_lt_sixt_dword = ~|bytes_to_transfer[TOTAL_BYTES_WIDTH-1:4] & ~dword_carry_double; + assign bytes_lt_sixt_qword = ~|bytes_to_transfer[TOTAL_BYTES_WIDTH-1:4] & ~qword_carry[4]; + assign bytes_lt_ttwo_qword = ~|bytes_to_transfer[TOTAL_BYTES_WIDTH-1:5] & ~qword_carry_double; + end + else if(DS_DATA_WIDTH == 256) + begin:bytes_lt_256 + assign bytes_lt_one_byte = ~|bytes_to_transfer; + assign bytes_lt_two_byte = ~|bytes_to_transfer[TOTAL_BYTES_WIDTH-1:1]; + assign bytes_lt_two_half = ~|bytes_to_transfer[TOTAL_BYTES_WIDTH-1:1] & ~half_carry; + assign bytes_lt_four_half = ~|bytes_to_transfer[TOTAL_BYTES_WIDTH-1:2] & ~half_carry_double; + assign bytes_lt_four_word = ~|bytes_to_transfer[TOTAL_BYTES_WIDTH-1:2] & ~word_carry[2]; + assign bytes_lt_eight_word = ~|bytes_to_transfer[TOTAL_BYTES_WIDTH-1:3] & ~word_carry_double; + assign bytes_lt_eight_dword = ~|bytes_to_transfer[TOTAL_BYTES_WIDTH-1:3] & ~dword_carry[3]; + assign bytes_lt_sixt_dword = ~|bytes_to_transfer[TOTAL_BYTES_WIDTH-1:4] & ~dword_carry_double; + assign bytes_lt_sixt_qword = ~|bytes_to_transfer[TOTAL_BYTES_WIDTH-1:4] & ~qword_carry[4]; + assign bytes_lt_ttwo_qword = ~|bytes_to_transfer[TOTAL_BYTES_WIDTH-1:5] & ~qword_carry_double; + assign bytes_lt_ttwo_oword = ~|bytes_to_transfer[TOTAL_BYTES_WIDTH-1:5] & ~oword_carry[5]; + assign bytes_lt_sfour_oword = ~|bytes_to_transfer[TOTAL_BYTES_WIDTH-1:6] & ~oword_carry_double; + end + else if(DS_DATA_WIDTH == 512) + begin:bytes_lt_512 + assign bytes_lt_one_byte = ~|bytes_to_transfer; + assign bytes_lt_two_byte = ~|bytes_to_transfer[TOTAL_BYTES_WIDTH-1:1]; + assign bytes_lt_two_half = ~|bytes_to_transfer[TOTAL_BYTES_WIDTH-1:1] & ~half_carry; + assign bytes_lt_four_half = ~|bytes_to_transfer[TOTAL_BYTES_WIDTH-1:2] & ~half_carry_double; + assign bytes_lt_four_word = ~|bytes_to_transfer[TOTAL_BYTES_WIDTH-1:2] & ~word_carry[2]; + assign bytes_lt_eight_word = ~|bytes_to_transfer[TOTAL_BYTES_WIDTH-1:3] & ~word_carry_double; + assign bytes_lt_eight_dword = ~|bytes_to_transfer[TOTAL_BYTES_WIDTH-1:3] & ~dword_carry[3]; + assign bytes_lt_sixt_dword = ~|bytes_to_transfer[TOTAL_BYTES_WIDTH-1:4] & ~dword_carry_double; + assign bytes_lt_sixt_qword = ~|bytes_to_transfer[TOTAL_BYTES_WIDTH-1:4] & ~qword_carry[4]; + assign bytes_lt_ttwo_qword = ~|bytes_to_transfer[TOTAL_BYTES_WIDTH-1:5] & ~qword_carry_double; + assign bytes_lt_ttwo_oword = ~|bytes_to_transfer[TOTAL_BYTES_WIDTH-1:5] & ~oword_carry[5]; + assign bytes_lt_sfour_oword = ~|bytes_to_transfer[TOTAL_BYTES_WIDTH-1:6] & ~oword_carry_double; + end + else + begin:bytes_lt_others + assign bytes_lt_one_byte = ~|bytes_to_transfer; + assign bytes_lt_two_byte = ~|bytes_to_transfer[TOTAL_BYTES_WIDTH-1:1]; + assign bytes_lt_two_half = ~|bytes_to_transfer[TOTAL_BYTES_WIDTH-1:1] & ~half_carry; + assign bytes_lt_four_half = ~|bytes_to_transfer[TOTAL_BYTES_WIDTH-1:2] & ~half_carry_double; + assign bytes_lt_four_word = ~|bytes_to_transfer[TOTAL_BYTES_WIDTH-1:2] & ~word_carry[2]; + assign bytes_lt_eight_word = ~|bytes_to_transfer[TOTAL_BYTES_WIDTH-1:3] & ~word_carry_double; + assign bytes_lt_eight_dword = ~|bytes_to_transfer[TOTAL_BYTES_WIDTH-1:3] & ~dword_carry[3]; + assign bytes_lt_sixt_dword = ~|bytes_to_transfer[TOTAL_BYTES_WIDTH-1:4] & ~dword_carry_double; + assign bytes_lt_sixt_qword = ~|bytes_to_transfer[TOTAL_BYTES_WIDTH-1:4] & ~qword_carry[4]; + assign bytes_lt_ttwo_qword = ~|bytes_to_transfer[TOTAL_BYTES_WIDTH-1:5] & ~qword_carry_double; + assign bytes_lt_ttwo_oword = ~|bytes_to_transfer[TOTAL_BYTES_WIDTH-1:5] & ~oword_carry[5]; + assign bytes_lt_sfour_oword = ~|bytes_to_transfer[TOTAL_BYTES_WIDTH-1:6] & ~oword_carry_double; + end +endgenerate +generate + if(DS_DATA_WIDTH == 32) + begin:incrsize_32 + always @(*) + begin : size_lookup + incrsize = DS_ADDR_AL_WIDTH; + if ((bytes_lt_one_byte || (bytes_lt_two_byte && (&offset_address[DS_ADDR_AL_WIDTH-1:0])))&&(DS_DATA_WIDTH>=16)) begin + incrsize = `AXI_ASIZE_8; + end else if ((bytes_lt_two_half || (bytes_lt_four_half && (&offset_address[DS_ADDR_AL_WIDTH-1:((DS_ADDR_AL_WIDTH>=2) ? 1:0)])))&&(DS_DATA_WIDTH>=32)) begin + incrsize = `AXI_ASIZE_16; + end else if ((bytes_lt_four_word || (bytes_lt_eight_word && (&offset_address[DS_ADDR_AL_WIDTH-1:((DS_ADDR_AL_WIDTH>=3) ? 2:0)])))&&(DS_DATA_WIDTH>=64)) begin + incrsize = `AXI_ASIZE_32; + end + end + end + else if(DS_DATA_WIDTH == 64) + begin:incrsize_64 + always @(*) + begin : size_lookup + incrsize = DS_ADDR_AL_WIDTH; + if ((bytes_lt_one_byte || (bytes_lt_two_byte && (&offset_address[DS_ADDR_AL_WIDTH-1:0])))&&(DS_DATA_WIDTH>=16)) begin + incrsize = `AXI_ASIZE_8; + end else if ((bytes_lt_two_half || (bytes_lt_four_half && (&offset_address[DS_ADDR_AL_WIDTH-1:((DS_ADDR_AL_WIDTH>=2) ? 1:0)])))&&(DS_DATA_WIDTH>=32)) begin + incrsize = `AXI_ASIZE_16; + end else if ((bytes_lt_four_word || (bytes_lt_eight_word && (&offset_address[DS_ADDR_AL_WIDTH-1:((DS_ADDR_AL_WIDTH>=3) ? 2:0)])))&&(DS_DATA_WIDTH>=64)) begin + incrsize = `AXI_ASIZE_32; + end else if ((bytes_lt_eight_dword || (bytes_lt_sixt_dword && (&offset_address[DS_ADDR_AL_WIDTH-1:((DS_ADDR_AL_WIDTH>=4) ? 3:0)])))&&(DS_DATA_WIDTH>=128)) begin + incrsize = `AXI_ASIZE_64; + end + end + end + else if(DS_DATA_WIDTH == 128) + begin:incrsize_128 + always @(*) + begin : size_lookup + incrsize = DS_ADDR_AL_WIDTH; + if ((bytes_lt_one_byte || (bytes_lt_two_byte && (&offset_address[DS_ADDR_AL_WIDTH-1:0])))&&(DS_DATA_WIDTH>=16)) begin + incrsize = `AXI_ASIZE_8; + end else if ((bytes_lt_two_half || (bytes_lt_four_half && (&offset_address[DS_ADDR_AL_WIDTH-1:((DS_ADDR_AL_WIDTH>=2) ? 1:0)])))&&(DS_DATA_WIDTH>=32)) begin + incrsize = `AXI_ASIZE_16; + end else if ((bytes_lt_four_word || (bytes_lt_eight_word && (&offset_address[DS_ADDR_AL_WIDTH-1:((DS_ADDR_AL_WIDTH>=3) ? 2:0)])))&&(DS_DATA_WIDTH>=64)) begin + incrsize = `AXI_ASIZE_32; + end else if ((bytes_lt_eight_dword || (bytes_lt_sixt_dword && (&offset_address[DS_ADDR_AL_WIDTH-1:((DS_ADDR_AL_WIDTH>=4) ? 3:0)])))&&(DS_DATA_WIDTH>=128)) begin + incrsize = `AXI_ASIZE_64; + end else if ((bytes_lt_sixt_qword || (bytes_lt_ttwo_qword && (&offset_address[DS_ADDR_AL_WIDTH-1:((DS_ADDR_AL_WIDTH>=5) ? 4:0)])))&&(DS_DATA_WIDTH>=256)) begin + incrsize = `AXI_ASIZE_128; + end + end + end + else if(DS_DATA_WIDTH == 256) + begin:incrsize_256 + always @(*) + begin : size_lookup + incrsize = DS_ADDR_AL_WIDTH; + if ((bytes_lt_one_byte || (bytes_lt_two_byte && (&offset_address[DS_ADDR_AL_WIDTH-1:0])))&&(DS_DATA_WIDTH>=16)) begin + incrsize = `AXI_ASIZE_8; + end else if ((bytes_lt_two_half || (bytes_lt_four_half && (&offset_address[DS_ADDR_AL_WIDTH-1:((DS_ADDR_AL_WIDTH>=2) ? 1:0)])))&&(DS_DATA_WIDTH>=32)) begin + incrsize = `AXI_ASIZE_16; + end else if ((bytes_lt_four_word || (bytes_lt_eight_word && (&offset_address[DS_ADDR_AL_WIDTH-1:((DS_ADDR_AL_WIDTH>=3) ? 2:0)])))&&(DS_DATA_WIDTH>=64)) begin + incrsize = `AXI_ASIZE_32; + end else if ((bytes_lt_eight_dword || (bytes_lt_sixt_dword && (&offset_address[DS_ADDR_AL_WIDTH-1:((DS_ADDR_AL_WIDTH>=4) ? 3:0)])))&&(DS_DATA_WIDTH>=128)) begin + incrsize = `AXI_ASIZE_64; + end else if ((bytes_lt_sixt_qword || (bytes_lt_ttwo_qword && (&offset_address[DS_ADDR_AL_WIDTH-1:((DS_ADDR_AL_WIDTH>=5) ? 4:0)])))&&(DS_DATA_WIDTH>=256)) begin + incrsize = `AXI_ASIZE_128; + end else if ((bytes_lt_ttwo_oword || (bytes_lt_sfour_oword && (&offset_address[DS_ADDR_AL_WIDTH-1:((DS_ADDR_AL_WIDTH>=6) ? 4:0)])))&&(DS_DATA_WIDTH>=512)) begin + incrsize = `AXI_ASIZE_256; + end + end + end + else if(DS_DATA_WIDTH == 512) + begin:incrsize_512 + always @(*) + begin : size_lookup + incrsize = DS_ADDR_AL_WIDTH; + if ((bytes_lt_one_byte || (bytes_lt_two_byte && (&offset_address[DS_ADDR_AL_WIDTH-1:0])))&&(DS_DATA_WIDTH>=16)) begin + incrsize = `AXI_ASIZE_8; + end else if ((bytes_lt_two_half || (bytes_lt_four_half && (&offset_address[DS_ADDR_AL_WIDTH-1:((DS_ADDR_AL_WIDTH>=2) ? 1:0)])))&&(DS_DATA_WIDTH>=32)) begin + incrsize = `AXI_ASIZE_16; + end else if ((bytes_lt_four_word || (bytes_lt_eight_word && (&offset_address[DS_ADDR_AL_WIDTH-1:((DS_ADDR_AL_WIDTH>=3) ? 2:0)])))&&(DS_DATA_WIDTH>=64)) begin + incrsize = `AXI_ASIZE_32; + end else if ((bytes_lt_eight_dword || (bytes_lt_sixt_dword && (&offset_address[DS_ADDR_AL_WIDTH-1:((DS_ADDR_AL_WIDTH>=4) ? 3:0)])))&&(DS_DATA_WIDTH>=128)) begin + incrsize = `AXI_ASIZE_64; + end else if ((bytes_lt_sixt_qword || (bytes_lt_ttwo_qword && (&offset_address[DS_ADDR_AL_WIDTH-1:((DS_ADDR_AL_WIDTH>=5) ? 4:0)])))&&(DS_DATA_WIDTH>=256)) begin + incrsize = `AXI_ASIZE_128; + end else if ((bytes_lt_ttwo_oword || (bytes_lt_sfour_oword && (&offset_address[DS_ADDR_AL_WIDTH-1:((DS_ADDR_AL_WIDTH>=6) ? 5:0)])))&&(DS_DATA_WIDTH>=512)) begin + incrsize = `AXI_ASIZE_256; + end + end + end + else + begin:incrsize_others + always @(*) + begin : size_lookup + incrsize = DS_ADDR_AL_WIDTH; + if ((bytes_lt_one_byte || (bytes_lt_two_byte && (&offset_address[DS_ADDR_AL_WIDTH-1:0])))&&(DS_DATA_WIDTH>=16)) begin + incrsize = `AXI_ASIZE_8; + end else if ((bytes_lt_two_half || (bytes_lt_four_half && (&offset_address[DS_ADDR_AL_WIDTH-1:((DS_ADDR_AL_WIDTH>=2) ? 1:0)])))&&(DS_DATA_WIDTH>=32)) begin + incrsize = `AXI_ASIZE_16; + end else if ((bytes_lt_four_word || (bytes_lt_eight_word && (&offset_address[DS_ADDR_AL_WIDTH-1:((DS_ADDR_AL_WIDTH>=3) ? 2:0)])))&&(DS_DATA_WIDTH>=64)) begin + incrsize = `AXI_ASIZE_32; + end else if ((bytes_lt_eight_dword || (bytes_lt_sixt_dword && (&offset_address[DS_ADDR_AL_WIDTH-1:((DS_ADDR_AL_WIDTH>=4) ? 3:0)])))&&(DS_DATA_WIDTH>=128)) begin + incrsize = `AXI_ASIZE_64; + end else if ((bytes_lt_sixt_qword || (bytes_lt_ttwo_qword && (&offset_address[DS_ADDR_AL_WIDTH-1:((DS_ADDR_AL_WIDTH>=5) ? 4:0)])))&&(DS_DATA_WIDTH>=256)) begin + incrsize = `AXI_ASIZE_128; + end else if ((bytes_lt_ttwo_oword || (bytes_lt_sfour_oword && (&offset_address[DS_ADDR_AL_WIDTH-1:((DS_ADDR_AL_WIDTH>=6) ? 4:0)])))&&(DS_DATA_WIDTH>=512)) begin + incrsize = `AXI_ASIZE_256; + end + end + end +endgenerate + assign final_address = {1'b0, offset_address} + {1'b0, bytes_to_transfer_large[DS_ADDR_AL_WIDTH-1:0]}; + assign overflow = final_address[DS_ADDR_AL_WIDTH]; + assign bytes_to_transfer_large = {8'h0, bytes_to_transfer}; + assign incrlenmaxsize = bytes_to_transfer_large[DS_ADDR_AL_WIDTH+:((DS_AXI3==1) ? 4 : 8)] + 4'b1; + assign incrlen = (overflow) ? incrlenmaxsize : ((DS_AXI3==1) ? {4'b0000,bytes_to_transfer_large[DS_ADDR_AL_WIDTH+:4]}:bytes_to_transfer_large[DS_ADDR_AL_WIDTH+:8]); + +endmodule +`include "Axi_undefs.v"
diff --git a/axi2sramcrs/rtl/upsizer/upsize_wr_cntrl.v b/axi2sramcrs/rtl/upsizer/upsize_wr_cntrl.v new file mode 100644 index 0000000..d887a1c --- /dev/null +++ b/axi2sramcrs/rtl/upsizer/upsize_wr_cntrl.v
@@ -0,0 +1,280 @@ +//**************************************************************************** +// +// Copyright 2017-2023 Vivante Corporation +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +//**************************************************************************** +// Auto-generated file on 11/03/2023. +// +//**************************************************************************** + +module upsize_wr_cntrl + ( + awfifo_ready, wready_s, merge, merge_clear, data_select, wvalid_m, + wdata_m, wstrb_m, wlast_m, wuser_m, wid_m, + aclk, aresetn, awfifo_valid, awfifo_data, wvalid_s, wlast, wuser, + wid, strb_skid_valid, wdata_merged, wstrb_merged, wready_m + ); +`include "Axi.v" +parameter ARID_WIDTH=4; +parameter AWID_WIDTH=4; +parameter ADDR_WIDTH=32; +parameter US_DATA_WIDTH=256; +parameter DS_DATA_WIDTH=128; +parameter USER_WIDTH=4; +localparam DS_WSTRB_WIDTH=DS_DATA_WIDTH/8; +localparam US_WSTRB_WIDTH=US_DATA_WIDTH/8; +localparam DS_ADDR_AL_WIDTH=$clog2(DS_WSTRB_WIDTH); +localparam US_ADDR_AL_WIDTH=$clog2(US_WSTRB_WIDTH); +localparam ARFMT_WIDTH=4+DS_ADDR_AL_WIDTH+US_ADDR_AL_WIDTH+3; +localparam AWFMT_WIDTH=AWID_WIDTH+1+4+1+DS_ADDR_AL_WIDTH*2+3+1; +localparam US_AW_WIDTH=4+USER_WIDTH+AWID_WIDTH+ADDR_WIDTH+8+3+2+2+4+4+3+1; +localparam US_AR_WIDTH=4+USER_WIDTH+ARID_WIDTH+ADDR_WIDTH+8+3+2+2+4+4+3+1; +localparam US_R_WIDTH=USER_WIDTH+ARID_WIDTH+US_DATA_WIDTH+2+1; +localparam US_W_WIDTH=USER_WIDTH+AWID_WIDTH+US_DATA_WIDTH+US_WSTRB_WIDTH+1; +localparam US_B_WIDTH=USER_WIDTH+AWID_WIDTH+2; +localparam AW_IDB_WIDTH=US_AW_WIDTH+US_ADDR_AL_WIDTH-DS_ADDR_AL_WIDTH; +localparam AR_IDB_WIDTH=US_AR_WIDTH+ARFMT_WIDTH; +localparam W_IDB_WIDTH=USER_WIDTH+US_DATA_WIDTH+US_WSTRB_WIDTH+1; +localparam R_IDB_WIDTH=USER_WIDTH+ARID_WIDTH+US_DATA_WIDTH+2+1+DS_ADDR_AL_WIDTH; +localparam B_IDB_WIDTH=USER_WIDTH+2+AWID_WIDTH; +localparam DATA_RATIO=(DS_DATA_WIDTH/US_DATA_WIDTH); + input aclk; + input aresetn; + output awfifo_ready; + input awfifo_valid; + input [AWFMT_WIDTH-1:0] awfifo_data; + input wvalid_s; + output wready_s; + input wlast; + input [USER_WIDTH-1:0] wuser; + input [AWID_WIDTH-1:0] wid; + output merge; + output merge_clear; + output [DATA_RATIO-1:0] data_select; + input strb_skid_valid; + input [DS_DATA_WIDTH-1:0] wdata_merged; + input [DS_WSTRB_WIDTH-1:0] wstrb_merged; + output wvalid_m; + input wready_m; + output [DS_DATA_WIDTH-1:0] wdata_m; + output [DS_WSTRB_WIDTH-1:0] wstrb_m; + output wlast_m; + output [USER_WIDTH-1:0] wuser_m; + output [AWID_WIDTH-1:0] wid_m; + wire slavew_hndshk; + wire wfifo_hndshk; + wire awfifo_hndshk; + wire bypass_in; + wire [2:0] write_size; + wire [DS_ADDR_AL_WIDTH-1:0] write_addr; + wire [DS_ADDR_AL_WIDTH-1:0] write_addr_mask; + wire [3:0] write_len_tb; + wire bypass; + wire [2:0] a_size; + wire [DS_ADDR_AL_WIDTH-1:0] addr_mask; + wire [DS_ADDR_AL_WIDTH-1:0] addr_internal; + wire [3:0] beat_count; + wire [DS_ADDR_AL_WIDTH:0] addr_incr; + wire [DS_ADDR_AL_WIDTH-1:0] store_addr; + wire [3:0] beat_reg_next; + wire beat_reg_wr_en; + wire wrap_fits_in; + wire wrap_fits; + wire split_wrap; + wire split_wrap_in; + wire split_wrap_reg_en; + wire split_wrap_reg_next; + wire cross_boundary; + wire cross_boundary_sel; + wire idle; + wire insert_extra_wlast; + wire wlast_sel; + wire wfifo_valid_next; + wire wfifo_should_push; + wire busy_reg_next; + wire reg_wr_en; + wire reg_update; + wire [AWID_WIDTH-1:0] wid_in; + reg [DS_ADDR_AL_WIDTH-1:0] addr_reg; + reg [DS_ADDR_AL_WIDTH-1:0] addr_mask_reg; + reg cross_boundary_reg; + reg [2:0] size_reg; + reg bypass_reg; + reg [3:0] beat_reg; + reg split_wrap_reg; + reg wrap_fits_reg; + reg [6:0] size_incr; + reg [DS_ADDR_AL_WIDTH-1:0] addr_reg_nxt; + wire [DATA_RATIO-1:0] data_select; + reg wfifo_valid_reg; + reg busy_reg; + reg merge_clear; + reg wlast_reg; + reg [USER_WIDTH-1:0] wuser_reg; + reg [AWID_WIDTH-1:0] wid_reg; + assign slavew_hndshk = wvalid_s && wready_s; + assign wfifo_hndshk = wvalid_m && wready_m; + assign awfifo_hndshk = awfifo_valid && awfifo_ready; + assign merge = slavew_hndshk; + always @(posedge aclk or negedge aresetn) + begin : last_clear_p + if (!aresetn) + merge_clear <= 1'b0; + else if (merge || wfifo_hndshk) + merge_clear <= wfifo_hndshk; + end + assign idle = (~awfifo_valid && ~busy_reg); +genvar i; +generate + for(i=0;i<DATA_RATIO;i=i+1) begin: for_data_select + assign data_select[i]=(idle) ? 1'h1 : (addr_internal[DS_ADDR_AL_WIDTH-1:US_ADDR_AL_WIDTH]==i); + end +endgenerate + assign wready_s = ~strb_skid_valid & ~wfifo_valid_reg; + assign awfifo_ready = ~busy_reg; + assign wfifo_valid_next = ((wvalid_m & ~wready_m) || wfifo_valid_reg) & ~wfifo_hndshk; + always @(posedge aclk or negedge aresetn) + begin : wfifo_valid_seq + if (!aresetn) + wfifo_valid_reg <= 1'b0; + else + wfifo_valid_reg <= wfifo_valid_next; + end + assign wfifo_should_push = (bypass || wlast_sel || cross_boundary_sel) & (busy_reg || awfifo_hndshk); + assign wvalid_m = wfifo_should_push & (wfifo_valid_reg || merge || strb_skid_valid); + assign reg_update = slavew_hndshk || (busy_reg_next && strb_skid_valid); + always @(posedge aclk or negedge aresetn) + begin : wfifo_data_int_seq + if (!aresetn) begin + wlast_reg <= 1'b0; + wuser_reg <= {USER_WIDTH{1'b0}}; + end else if (slavew_hndshk) begin + wlast_reg <= wlast; + wuser_reg <= wuser; + end + end + always @(posedge aclk or negedge aresetn) + begin : cross_boundary_reg_seq + if (!aresetn) begin + cross_boundary_reg <= 1'b0; + end else if (reg_update) begin + cross_boundary_reg <= cross_boundary; + end + end + assign wlast_sel = (wready_s) ? (wlast & wvalid_s) : wlast_reg; + assign cross_boundary_sel = (wfifo_valid_reg) ? cross_boundary_reg : cross_boundary; + assign busy_reg_next = ((awfifo_hndshk & ~(strb_skid_valid & wfifo_valid_reg) & ~(wlast_sel & wfifo_hndshk))) ? 1'b1 : + ((wfifo_hndshk & wlast_sel) ? 1'b0 : busy_reg); + always @(posedge aclk or negedge aresetn) + begin : busy_seq + if (!aresetn) + busy_reg <= 1'b0; + else + busy_reg <= busy_reg_next; + end +assign { + wid_in, + split_wrap_in, + write_len_tb, + wrap_fits_in, + write_addr_mask, + write_addr, + write_size, + bypass_in + } = awfifo_data; + assign wlast_m = wlast_sel || insert_extra_wlast; + assign wid_m = (awfifo_valid ? wid_in : wid_reg); + assign wuser_m = (wfifo_valid_reg || strb_skid_valid) ? wuser_reg : wuser; + assign wdata_m = wdata_merged; + assign wstrb_m = wstrb_merged; + assign insert_extra_wlast = (~|beat_count & ~bypass & split_wrap); + assign beat_reg_next = (|beat_count & wfifo_hndshk) ? beat_count - 4'b1 : beat_count; + assign beat_reg_wr_en = (wfifo_hndshk || awfifo_hndshk)& split_wrap; + always @(posedge aclk or negedge aresetn) + begin : beat_cnt_p + if (!aresetn) + beat_reg <= 4'b0; + else if (beat_reg_wr_en) + beat_reg <= beat_reg_next; + end + assign split_wrap_reg_en = awfifo_hndshk || (insert_extra_wlast & wfifo_hndshk); + assign split_wrap_reg_next = split_wrap & ~(insert_extra_wlast & wfifo_hndshk); + always @(posedge aclk or negedge aresetn) + begin : unaligned_p + if (!aresetn) + split_wrap_reg <= 1'b0; + else if (split_wrap_reg_en) + split_wrap_reg <= split_wrap_reg_next; + end + assign addr_internal = (awfifo_hndshk) ? write_addr : addr_reg; + assign addr_mask = (awfifo_hndshk) ? write_addr_mask : addr_mask_reg; + assign bypass = (awfifo_hndshk) ? bypass_in : bypass_reg; + assign a_size = (awfifo_hndshk) ? write_size : size_reg; + assign wrap_fits = (awfifo_hndshk) ? wrap_fits_in : wrap_fits_reg; + assign beat_count = (awfifo_hndshk) ? write_len_tb : beat_reg; + assign split_wrap = (awfifo_hndshk) ? split_wrap_in : split_wrap_reg; + always @(*) + begin : size_incr_p + case (a_size) + `AXI_ASIZE_8 : size_incr = {6'b0, 1'b1}; + `AXI_ASIZE_16 : size_incr = {5'b0, 2'b10}; + `AXI_ASIZE_32 : size_incr = {4'b0, 3'b100}; + `AXI_ASIZE_64 : size_incr = {3'b0, 4'b1000}; + `AXI_ASIZE_128 : size_incr = {2'b0, 5'b10000}; + `AXI_ASIZE_256 : size_incr = {1'b0, 6'b100000}; + `AXI_ASIZE_512 : size_incr = {7'b1000000}; + default : size_incr = {7'bx}; + endcase + end + assign addr_incr = {1'b0, addr_internal} + size_incr[DS_ADDR_AL_WIDTH:0]; + always @(*) + begin : addr_reg_nxt_p + integer index_i; + for (index_i = 0; index_i < DS_ADDR_AL_WIDTH ; index_i = index_i + 1) + begin + if (addr_mask[index_i] == 1'b1) + addr_reg_nxt[index_i] = addr_incr[index_i]; + else + addr_reg_nxt[index_i] = addr_internal[index_i]; + end + end + assign store_addr = (reg_update) ? addr_reg_nxt : addr_internal; + assign reg_wr_en = merge || awfifo_hndshk; + always @(posedge aclk or negedge aresetn) + begin : addr_seq + if (!aresetn) + addr_reg <= {DS_ADDR_AL_WIDTH{1'b0}}; + else if (reg_wr_en) + addr_reg <= store_addr; + end + always @(posedge aclk or negedge aresetn) + begin : store_seq + if (!aresetn) begin + addr_mask_reg <= {DS_ADDR_AL_WIDTH{1'b0}}; + wid_reg <= {AWID_WIDTH{1'b0}}; + bypass_reg <= 1'b0; + size_reg <= 3'b0; + wrap_fits_reg <= 1'b0; + end else if (awfifo_hndshk) begin + addr_mask_reg <= write_addr_mask; + wid_reg <= wid_in; + bypass_reg <= bypass_in; + size_reg <= write_size; + wrap_fits_reg <= wrap_fits_in; + end + end + assign cross_boundary = (|((addr_incr ^ {1'b0, addr_internal}) & ({1'b1, ~addr_mask} ))) & ~(wrap_fits); +endmodule +`include "Axi_undefs.v"
diff --git a/axi2sramcrs/rtl/upsizer/upsize_wr_merge_buffer.v b/axi2sramcrs/rtl/upsizer/upsize_wr_merge_buffer.v new file mode 100644 index 0000000..bdd3b0a --- /dev/null +++ b/axi2sramcrs/rtl/upsizer/upsize_wr_merge_buffer.v
@@ -0,0 +1,102 @@ +//**************************************************************************** +// +// Copyright 2017-2023 Vivante Corporation +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +//**************************************************************************** +// Auto-generated file on 11/03/2023. +// +//**************************************************************************** + +module upsize_wr_merge_buffer + ( + wdata_out, + wstrb_out, + merge_skid_valid, + wdata_in, + wstrb_in, + data_select, + merge, + merge_clear, + aclk, + aresetn + ); +parameter US_DATA_WIDTH=128; +parameter DS_DATA_WIDTH=256; +localparam US_WSTRB_WIDTH=US_DATA_WIDTH/8; +localparam DS_WSTRB_WIDTH=DS_DATA_WIDTH/8; +localparam DATA_RATIO=(DS_DATA_WIDTH/US_DATA_WIDTH); + input aclk; + input aresetn; + output [DS_DATA_WIDTH-1:0] wdata_out; + output [DS_WSTRB_WIDTH-1:0] wstrb_out; + output merge_skid_valid; + input [US_DATA_WIDTH-1:0] wdata_in; + input [US_WSTRB_WIDTH-1:0] wstrb_in; + input [DATA_RATIO-1:0] data_select; + input merge; + input merge_clear; + wire [DS_DATA_WIDTH-1:0] wide_wdata_in; + wire [DS_WSTRB_WIDTH-1:0] wide_wstrb_in; + wire [DS_WSTRB_WIDTH-1:0] wide_wstrb_masked; + wire [DS_WSTRB_WIDTH-1:0] wstrb_out_i; + wire update_strb; + wire strb_skid_valid_wr; + wire strb_skid_valid_nxt; + wire all_bytes; + wire [DS_WSTRB_WIDTH-1:0] merge_byte,merge_strb,next_strb; + reg strb_skid_valid; + reg [7:0] merged_byte[DS_WSTRB_WIDTH-1:0]; + reg merged_strb[DS_WSTRB_WIDTH-1:0]; + assign wide_wdata_in = {DATA_RATIO{wdata_in}}; + assign wide_wstrb_masked = {DATA_RATIO{wstrb_in}} | {DS_WSTRB_WIDTH{all_bytes}}; + assign wide_wstrb_in = {DATA_RATIO{wstrb_in}}; + assign all_bytes = data_select == {DATA_RATIO{1'b1}}; + assign update_strb = merge_clear || (merge && all_bytes) + || (~all_bytes && strb_skid_valid); + assign strb_skid_valid_wr = (merge && all_bytes) || update_strb; + assign strb_skid_valid_nxt = merge && all_bytes; + always @(posedge aclk or negedge aresetn) + begin : strb_skid_valid_p + if (!aresetn) + strb_skid_valid <= 1'b0; + else if (strb_skid_valid_wr) + strb_skid_valid <= strb_skid_valid_nxt; + end + assign merge_skid_valid = strb_skid_valid; +genvar i; +generate + for(i=0;i<DS_WSTRB_WIDTH;i=i+1) begin:merge_byte_g + assign merge_byte[i]=merge && data_select[i/US_WSTRB_WIDTH] && wide_wstrb_masked[i]; + assign wdata_out[i*8+:8]=merge_byte[i] ? wide_wdata_in[i*8+:8] : merged_byte[i]; + assign merge_strb[i]=merge_byte[i] | update_strb; + assign wstrb_out_i[i] = merge_byte[i] ? wide_wstrb_in[i] : + (((strb_skid_valid && data_select[i/US_WSTRB_WIDTH]) || (~strb_skid_valid && ~update_strb)) ? merged_strb[i] : 1'b0); + assign wstrb_out[i] = wstrb_out_i[i]; + assign next_strb[i] = wstrb_out_i[i]; + always @(posedge aclk) + begin : byte_seq + if (merge_byte[i]) + merged_byte[i] <= wide_wdata_in[i*8+:8]; + end + always @(posedge aclk or negedge aresetn) + begin : byte_strb_seq + if (!aresetn) + merged_strb[i] <= 1'b0; + else if (merge_strb[i]) + merged_strb[i] <= next_strb[i]; + end + end +endgenerate +endmodule
diff --git a/axi2sramcrs/rtl/upsizer/upsize_wr_resp_block.v b/axi2sramcrs/rtl/upsizer/upsize_wr_resp_block.v new file mode 100644 index 0000000..4e9ebfb --- /dev/null +++ b/axi2sramcrs/rtl/upsizer/upsize_wr_resp_block.v
@@ -0,0 +1,170 @@ +//**************************************************************************** +// +// Copyright 2017-2023 Vivante Corporation +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +//**************************************************************************** +// Auto-generated file on 11/03/2023. +// +//**************************************************************************** + +module upsize_wr_resp_block + ( + bchannel_ready, bvalid_s, bready_m, bid_s, bresp_s, buser_s, + aclk, aresetn, bvalid_m, bready_s, bid_m, bresp_m, buser_m, + bchannel_valid, bchannel_data + ); +parameter AWID_WIDTH=4; +parameter USER_WIDTH=4; +parameter WR_ISS=8; +localparam PTR_WIDTH=$clog2(WR_ISS+1); +localparam BCHAN_WIDTH=AWID_WIDTH+1; + input aclk; + input aresetn; + output bchannel_ready; + output bvalid_s; + output bready_m; + output [AWID_WIDTH-1:0] bid_s; + output [1:0] bresp_s; + output [USER_WIDTH-1:0] buser_s; + input bvalid_m; + input bready_s; + input [AWID_WIDTH-1:0] bid_m; + input [1:0] bresp_m; + input [USER_WIDTH-1:0] buser_m; + input bchannel_valid; + input [BCHAN_WIDTH-1:0] bchannel_data; + wire [WR_ISS-1:0] match_bus; + wire [WR_ISS-1:0] hazard_bus; + wire [WR_ISS-1:0] valid_bus; + wire [WR_ISS-1:0] valid_bus_zero_lsb; + wire [PTR_WIDTH-1:0] hazard_bus_one_pos[WR_ISS-1:0]; + wire [PTR_WIDTH-1:0] match_bus_one_pos[WR_ISS-1:0]; + wire match; + wire hazard; + wire bready_m_i; + wire bhndshk; + wire push_slice; + wire pop_slice; + wire update; + wire [AWID_WIDTH-1:0] awid; + wire n_response; + wire next_bchannel_ready; + wire [1:0] bresp_out[WR_ISS-1:0]; + wire [WR_ISS-1:0] const_onehot[WR_ISS-1:0]; + reg [PTR_WIDTH-1:0] hazard_pointer; + reg [PTR_WIDTH-1:0] match_pointer; + reg [WR_ISS-1:0] store; + reg bchannel_ready_i; + reg [1:0] bresp_out_or; + assign { + awid, + n_response + }=bchannel_data; + assign match = |match_bus; + assign hazard = |hazard_bus; + assign next_bchannel_ready = ~(&(valid_bus | (store & {WR_ISS{push_slice}}))) || (pop_slice); + always @(posedge aclk or negedge aresetn) + begin : bchannel_seq + if (!aresetn) + bchannel_ready_i <= 1'b0; + else + bchannel_ready_i <= next_bchannel_ready; + end + assign bchannel_ready = bchannel_ready_i; +genvar i; +generate + for(i=0;i<WR_ISS;i=i+1) begin: for_store + if(WR_ISS==1) begin: wr_iss_1 + assign const_onehot[i]=(1'h1<<i); + end + else begin: wr_iss_n + assign const_onehot[i]=({{(WR_ISS-1){1'h0}},1'h1}<<i); + end + assign valid_bus_zero_lsb[i]=((~valid_bus[i:0])==const_onehot[i][i:0]); + assign hazard_bus_one_pos[i]={PTR_WIDTH{hazard_bus[i]}}&i; + assign match_bus_one_pos[i]={PTR_WIDTH{match_bus[i]}}&i; + always @(*) + begin : store_decode + if (&valid_bus) + store[i] = match_bus[i]; + else + store[i] = valid_bus_zero_lsb[i]; + end + end +endgenerate + always @(*) + begin : hazard_num_distibution + integer a; + hazard_pointer={PTR_WIDTH{1'h0}}; + for(a=0;a<WR_ISS;a=a+1) begin + hazard_pointer=hazard_pointer | hazard_bus_one_pos[a]; + end + end + always @(*) + begin : match_num_distibution + integer a; + match_pointer={PTR_WIDTH{1'h0}}; + for(a=0;a<WR_ISS;a=a+1) begin + match_pointer=match_pointer | match_bus_one_pos[a]; + end + end + assign push_slice = bchannel_ready_i && bchannel_valid; + assign bhndshk = bvalid_m && bready_m_i; + assign update = bhndshk; + assign pop_slice = update && match; + assign bready_m_i = bvalid_m && (bready_s || ~match); + assign bready_m = bready_m_i; + assign bid_s = bid_m; + assign buser_s=buser_m; + always @(*) + begin:bresp_a + integer a; + bresp_out_or={2{1'h0}}; + for(a=0;a<WR_ISS;a=a+1) begin + bresp_out_or=bresp_out_or | bresp_out[a]; + end + end + assign bresp_s = (bresp_m + | bresp_out_or ); + assign bvalid_s = (bvalid_m && match); +generate +for(i=0;i<WR_ISS;i=i+1) begin: resp_cam_slice_inst + upsize_resp_cam_slice #( + .ID_WIDTH(AWID_WIDTH), + .USER_WIDTH(USER_WIDTH), + .PTR_WIDTH(PTR_WIDTH) + ) u_upsize_resp_cam_slice + ( + .aresetn (aresetn), + .aclk (aclk), + .matchid (bid_m), + .hazardid (awid), + .store (store[i]), + .push_slice (push_slice), + .pop_slice (pop_slice), + .update (update), + .match_pointer (match_pointer), + .hazard_in (hazard), + .hazard_pointer (hazard_pointer), + .n_response (n_response), + .bresp_in (bresp_m), + .hazard (hazard_bus[i]), + .match (match_bus[i]), + .valid (valid_bus[i]), + .bresp_out (bresp_out[i]) + ); +end +endgenerate +endmodule