tree 67d9b594336095d150c2ed41bd33c33957d0f61e
parent 8915a426624d4be17b50620934a3dce98a5a8f0e
author Hugo McNally <hugo.mcnally@gmail.com> 1732013931 +0000
committer Hugo McNally <45573837+HU90m@users.noreply.github.com> 1736200104 +0000

sonata: v1.0 SPI block driver

1. CS lines are now controlled by a register in the SPI controller
   itself.
2. FIFO depths are now available in the 'info' register, and the FIFOs
   are reduced to 16 entries apiece.
3. Ensure that zero-byte transfer requests do not result in a deadlock
   between software and hardware; the controller will attempt to start
   but cannot perform a zero-byte transfer.
    *  Zero-byte blocking_write/read can be used instead to synchronise
       with the controller core.
4. Interrupts for the SPI block added.
5. Added internal loopback. Internal loopback within the SPI controller
   is trivial and very useful for testing; simultaneous transmit and
   receive shall result in all transmitted bytes being replicated
   exactly in the receive FIFO; we can test permutations of polarity and
   phase settings.
6. Added software reset. Software reset is required to recover in the
   event of an error or indeed just a re-download of the software
   without an intervening IP block reset presently. Clear the TX FIFO,
   reset the controller core and then clear the RX FIFO.

Co-authored-by: Adrian Lees <a.lees@lowrisc.org>