)]}'
{
  "commit": "50064c929b323d4863b53bf5aa94df9765c69c9d",
  "tree": "67d9b594336095d150c2ed41bd33c33957d0f61e",
  "parents": [
    "8915a426624d4be17b50620934a3dce98a5a8f0e"
  ],
  "author": {
    "name": "Hugo McNally",
    "email": "hugo.mcnally@gmail.com",
    "time": "Tue Nov 19 10:58:51 2024 +0000"
  },
  "committer": {
    "name": "Hugo McNally",
    "email": "45573837+HU90m@users.noreply.github.com",
    "time": "Mon Jan 06 21:48:24 2025 +0000"
  },
  "message": "sonata: v1.0 SPI block driver\n\n1. CS lines are now controlled by a register in the SPI controller\n   itself.\n2. FIFO depths are now available in the \u0027info\u0027 register, and the FIFOs\n   are reduced to 16 entries apiece.\n3. Ensure that zero-byte transfer requests do not result in a deadlock\n   between software and hardware; the controller will attempt to start\n   but cannot perform a zero-byte transfer.\n    *  Zero-byte blocking_write/read can be used instead to synchronise\n       with the controller core.\n4. Interrupts for the SPI block added.\n5. Added internal loopback. Internal loopback within the SPI controller\n   is trivial and very useful for testing; simultaneous transmit and\n   receive shall result in all transmitted bytes being replicated\n   exactly in the receive FIFO; we can test permutations of polarity and\n   phase settings.\n6. Added software reset. Software reset is required to recover in the\n   event of an error or indeed just a re-download of the software\n   without an intervening IP block reset presently. Clear the TX FIFO,\n   reset the controller core and then clear the RX FIFO.\n\nCo-authored-by: Adrian Lees \u003ca.lees@lowrisc.org\u003e\n",
  "tree_diff": [
    {
      "type": "add",
      "old_id": "0000000000000000000000000000000000000000",
      "old_mode": 0,
      "old_path": "/dev/null",
      "new_id": "45ebce4aa98ce09c10220c7a5201747b76249edb",
      "new_mode": 33188,
      "new_path": "sdk/include/platform/sunburst/platform-spi.hh"
    }
  ]
}